Datasheet

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 108 © 2007-2012 Microchip Technology Inc.
REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
— RTCIE DMA5IE DCIIE DCIEIE — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12 DCIIE: DCI Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 11 DCIEIE: DCI Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 10-0 Unimplemented: Read as ‘0’