Information

© 2008 Microchip Technology Inc. DS80371B-page 3
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04
4. Module: SPI
The SPI module will generate incorrect frame
synchronization pulses when configured in Frame
Master mode if the start of data is selected to
coincide with the start of the frame synchronization
pulse (FRMEN = 1, SPIFSD = 0, FRMDLY = 1).
However, the module functions correctly in Frame
Slave mode, and also in Frame Master mode if
FRMDLY = 0.
Work around
If DMA is not being used, manually drive the SSx
pin (x = 1 or 2) high using the associated PORT
register, and then drive it low after the required
1 bit time pulse-width. This operation needs to be
performed when the transmit buffer is written.
If DMA is being used, and if no other peripheral
modules are using DMA transfers, use a timer
interrupt to periodically generate the frame
synchronization pulse (using the method
described above) after every 8 or 16-bit periods
(depending on the data word size, configured
using the MODE16 bit).
If FRMDLY = 0, no work around is needed.
5. Module: I
2
C
The BCL bit in I2CSTAT can only be cleared with
Word instructions, and can be corrupted with byte
instructions and bit operations.
Work around
Use Word instructions to clear BCL.
6. Module: I
2
C
During I
2
C communication, after a device
operating in Slave mode transmits data to the
master, the ACKSTAT bit in the I2CxSTAT register
is set or cleared depending on whether the master
sent an ACK or NACK after the byte of data. If the
ACKSTAT bit is set, it will be cleared again after
some delay.
Work around
Store the value of the ACKSTAT bit immediately
after an I
2
C interrupt occurs.
7. Module: I
2
C
If there are two I
2
C devices on the bus, one of
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are
configured for 10-bit addressing mode, and have
the same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
2
C devices, the addresses as well as bits
A10 and A9 should be different.
8. Module: I
2
C
When the I
2
C module is configured as a 10-bit
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02; however, the module
acknowledges both address bytes.
Work around
None.
9. Module: I
2
C
With the I
2
C module enabled, the PORT bits and
external interrupt input functions (if any)
associated with the SCL and SDA pins do not
reflect the actual digital logic levels on the pins.
Work around
If the SDA and/or SCL pins need to be polled,
these pins should be connected to other port pins
in order to be read correctly. This issue does not
affect the operation of the I
2
C module.
10. Module: I
2
C
In 10-bit Addressing mode, some address
matches don’t set the RBF flag or load the receive
register I2CxRCV, if the lower address byte
matches the reserved addresses. In particular,
these include all addresses with the form
XX0000XXXX and XX1111XXXX, with the
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.