Datasheet

© 2007-2012 Microchip Technology Inc. DS70283K-page 317
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
Revision H (February 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
instances of V
DDCORE have been removed.
All other major changes are referenced by their
respective section in the following table.
TABLE A-6: MAJOR SECTION UPDATES
Section Name Update Description
High-Performance, 16-bit Digital Signal
Controllers
Added the SSOP package information (see “Packaging:”, Table 1,
and “Pin Diagrams”).
Section 2.0 “Guidelines for Getting Started
with 16-bit Digital Signal Controllers”
Updated the title of Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”.
The frequency limitation for device PLL start-up conditions was
updated in Section 2.7 “Oscillator Value Conditions on Device
Start-up”.
The second paragraph in Section 2.9 “Unused I/Os” was updated.
Section 3.0 “CPU” Removed references to DMA in the CPU Core Block Diagram (see
Figure 3-1).
Section 4.0 “Memory Organization” Updated the data memory reference in the third paragraph in
Section 4.2 “Data Address Space”.
All Resets values for the following SFRs in the Timer Register Map
were changed (see Table 4-5):
•TMR1
•TMR2
•TMR3
Section 8.0 “Oscillator Configuration” Added Note 3 to the OSCCON: Oscillator Control Register (see
Register 8-1).
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register 8-2).
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register 8-3).
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register 8-4).
Section 20.0 “10-bit/12-bit Analog-to-Digital
Converter (ADC)”
Updated the V
REFL references in the ADC1 module block diagrams
(see Figure 20-1 and Figure 20-2).
Section 21.0 “Special Features” Added a new paragraph and removed the third paragraph in
Section 21.1 “Configuration Bits”.
Added the column “RTSP Effects” to the Configuration Bits
Descriptions (see Table 21-2).