Datasheet

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
DS70283K-page 200 © 2007-2012 Microchip Technology Inc.
FIGURE 20-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ16MC304 AND
dsPIC33FJ32MC204 DEVICES
SAR ADC
S/H0
S/H1
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0
AN8
AN1
VREFL
CH0SB<4:0>
CH0NA
CH0NB
+
-
AN0
AN3
CH123SA
VREFL
CH123SB
CH123NA
CH123NB
AN6
+
-
S/H2
AN1
AN4
CH123SA
VREFL
CH123SB
CH123NA
CH123NB
AN7
+
-
S/H3
AN2
AN5
CH123SA
VREFL
CH123SB
CH123NA
CH123NB
AN8
+
-
CH0
CH0SA<4:0>
CHANNEL
SCAN
CSCNA
Alternate
Input Selection
V
REFH
VREFL
CH1
(2)
CH2
(2)
CH3
(2)
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
AVDD
AVSS
VREF-
(1)
VREF+
(1)
VCFG<2:0>