dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 16-bit Digital Signal Controllers (up to 32 KB Flash and 2 KB SRAM) with Motor Control and Advanced Analog Operating Conditions • Six analog inputs on 28-pin devices and up to nine analog inputs on 44-pin devices • Flexible and independent ADC trigger sources • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS Timers/Output Compare/Input Capture Core: 16-bit dsPIC33F CPU • • • • • Three 16-bit timers/counters.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams 28-PIN SPDIP, SOIC, SSOP = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ32MC202 MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 SOSCI/RP4(1)/CN1/RB4 SOSCO/T1CK/CN0/RA4 VDD PGED3/ASDA1/RP5(1)/CN27/RB5 28 27 26 25 24 AVDD AVSS PWM1L1/RP15(1)/CN11/RB15 PWM1H1/RP14(1)/CN12/RB14 PWM1L2/RP13(1)/CN
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams (Continued) 44-Pin QFN(2) TMS/RA10 TCK/RA7 PWM1H1/RP14(1)/CN12/RB14 PWM1L1/RP15(1)/CN11/RB15 AVSS MCLR AVDD AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/EMUD1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/EMUC1/AN3/C2IN+/RP1(1)/CN5/RB1 = Pins are up to 5V tolerant 22 21 20 19 18 17 16 15 14 13 12 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/RP18(1)/CN10/RC2 11 24 10 25 9 26 8 PGED2/EMUD2/PWM1H3/RP10(1)/CN16/RB10
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams (Continued) 44-Pin TQFP PGEC1/EMUC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/EMUD1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS PWM1L1/RP15(1)/CN11/RB15 PWM1H1/RP14(1)/CN12/RB14 TCK/RA7 TMS/RA10 = Pins are up to 5V tolerant 12 13 14 15 16 17 18 19 20 21 22 11 10 9 8 7 6 5 4 3 2 1 PWM1L2/RP13(1)/CN13/RB13 PWM1H2/RP12(1)/CN14/RB12 PGEC2/EMUC2/PWM1L3/RP11(1)/CN15/RB11 PGED2/EMUD2/PWM1H3/RP10(1)/CN16/RB10 VCAP VSS RP25(1)/CN19/RC9
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Table of Contents dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families.................................................................................................. 2 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers ..........................
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ32MC204 product page of the Microchip web site (www.microchip.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 PORTB 16 23 16 16 PORTC Address Generator Units Address Latch Program Memory Remappable EA MUX Data Latch ROM Latch 24 FRC/LPRC Oscil
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS Pin Type Buffer Type PPS Description AN0-AN8 I Analog No Analog input channels. CLKI CLKO I O ST/CMOS — No No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS INDX QEA I I ST ST Yes Yes QEB I ST Yes UPDN O CMOS Yes Quadrature Encoder Index Pulse input. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum R R1 VSS VDD 2.4 VCAP VDD • Device Reset • Device programming and debugging C dsPIC33F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤8 MHz for start-up with PLL enabled. This means that if the external oscillator frequency is outside this range, the application must start-up in FRC mode first.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.0 CPU Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.3 Special MCU Features The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 3-2: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.4 CPU Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 3.4.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Inter
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 3-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit 0’ = Bit is cleared bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: U-0 — R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATA bit 7 bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER R/W-1 SATDW R/W-0 ACCSAT C = Clear only bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.6 Arithmetic Logic Unit (ALU) The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 Zero Backfill 16 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.7.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 3.7.3.2 Data Space Write Saturation 3.7.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 MEMORY ORGANIZATION Note: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Program Memory” (DS70202) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.2 Data Address Space The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DEVICES WITH 2 KB RAM MSB Address MSb 2 Kbyte SFR Space 2 Kbyte SRAM Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x0BFF 0x0001 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x0BFE 0x0C00 0x0FFF 0x1001 0x0FFE 0x1000 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8 Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70283K-page 32 LSB Ad
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.2.5 X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
Special Function Register Maps TABLE 4-1: SFR Name CPU CORE REGISTERS MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets © 2007-2012 Microchip Technology Inc.
CPU CORE REGISTERS MAP (CONTINUED) Bit 0 All Resets XS<15:1> 0 xxxx 004A XE<15:1> 1 xxxx 004C YS<15:1> 0 xxxx YE<15:1> 1 xxxx SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 MODCON 0046 XMODEN YMODEN — — XMODSRT 0048 XMODEND YMODSRT YMODEND 004E XBREV 0050 BREN DISICNT 0052 — SFR Name Legend: Bit 10 Bit 9 Bit 8 Bit 7 BWM<3:0> Bit 6 Bit 5 Bit 4 Bit 3 YWM<3:0> Bit 2 Bit 1 XWM<3:0> 0000 XB<14:0> — xxxx Disable Interrupts Counter Register xxxx x = unknown value on R
SFR Name SFR Addr INTERRUPT CONTROLLER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 MATHERR ADDRERR STKERR Bit 0 All Resets 0000 INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE OSCFAIL — INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 IFS0 0084 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 SFTACER
SFR Name TIMER REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TMR2 0106 Timer2 Register 0000 TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx TMR3 010A Timer3 Register 0000 PR2 010C Period Register 2 FFFF PR3 010E Period Register 3 T2CON 0110 TON — TSIDL — — — — — — TGATE
SFR Name Addr.
SFR Name QEI1 REGISTER MAP Bit 10 Addr.
ADC1 REGISTER MAP FOR dsPIC33FJ32MC202 Bit 15 Addr ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC Data Buffer 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8 xxxx ADC1BUF9 0312 ADC Data Buffer 9 xxxx ADC1BUFA 0314 ADC Data Buffer 10 xxxx ADC1BUF
ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 Addr ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC Data Buffer 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8 xxxx ADC1BUF9 0312 ADC Data Buffer 9 xxxx ADC1BUFA 0314 ADC Data Buffer 10
File Name Addr PERIPHERAL PIN SELECT INPUT REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 — — Bit 10 Bit 9 Bit 8 — — Bit 2 Bit 1 Bit 0 All Resets — — — 1F00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — — — — — — INT2R<4:0> 001F RPINR0 0680 — — — RPINR1 0682 — — — RPINR3 0686 — — — T3CKR<4:0> — — — T2CKR<4:0> 1F1F RPINR7 068E — — — IC2R<4:0> — — — IC1R<4:0> 1F1F RPINR10 0694 — — — — — — IC7R<4:0> 1F1F RPINR11 0696 — — — — — — — —
File Name PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 Addr Bit 15 Bit 14 Bit 13 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — RPOR3 06C6 — RPOR4 06C8 RPOR5 Bit 7 Bit 6 Bit 5 RP1R<4:0> — — — RP0R<4:0> 0000 RP3R<4:0> — — — RP2R<4:0> 0000 — RP5R<4:0> — — — RP4R<4:0> 0000 — — RP7R<4:0> — — — RP6R<4:0> 0000 — — — RP9R<4:0> — — — RP8R<4:0> 0000 06CA — — — RP11R<4:0> — — — RP10R<4:0> 0000 RPOR6 06
File Name PORTB REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB6 TRISB5 TRISB1 TRISB0 FFFF PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB6 RB5 RB1 RB0 xxxx LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6
NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — — — ERASE — — — Bit 4 Bit 3 NVMCON 0760 WR WREN WRERR — — — NVMKEY 0766 — — — — — — Legend: Note 1: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.4.1 SOFTWARE STACK 4.4.2 In addition to its use as a working register, the W15 register in the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 4-26: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Description The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.6 Modulo Addressing Note: Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.6.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 4-6: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address A3 A2 A1 A0 Bit-Reversed Address Decimal A3 A2 A1 A0 Decimal 0 0 0
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.8 Interfacing Program and Data Memory Spaces 4.8.1 The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space Visibility(1) (Remapping) 0 1 EA 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data s
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.8.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 4.8.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 5.0 FLASH PROGRAM MEMORY customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 5.2 RTSP Operation The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 24-12 shows typical erase and programming times.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 R/W-0(1) U-0 — U-0 ERASE — R/W-0(1) U-0 R/W-0(1) R/W-0(1) R/W-0(1) (2) — NVMOP<3:0> bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write C
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70283K-page
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ;
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure 6-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.1 Resets Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 6.1.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: 2: All of the Reset status bits can be set or cleared in software.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.3 System Reset • Cold Reset • Warm Reset A warm Reset is the result of all other reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection bits (COSC<2:0>) in the Oscillator Control register (OSCCON<14:12>). A cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 6-2: SYSTEM RESET TIMING VBOR Vbor VPOR VDD TPOR POR BOR 1 TBOR 2 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Device Status Reset Run Time Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 6-2: OSCILLATOR DELAY Symbol Parameter Value VPOR POR threshold TPOR POR extension time 1.8V nominal 30 μs maximum VBOR BOR threshold 2.5V nominal TBOR BOR extension time 100 μs maximum TPWRT Programmable power-up time delay 0-128 ms nominal TFSCM Fail-Safe Clock Monitor Delay 900 μs maximum Note: 6.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 6-3: BROWN-OUT SITUATIONS VDD VBOR TBOR + TPWRT SYSRST VDD VBOR TBOR + TPWRT SYSRST VDD dips before PWRT expires VDD VBOR TBOR + TPWRT SYSRST 6.5 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse-width will generate a Reset. Refer to Section 24.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 6.9 Configuration Mismatch Reset each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value. To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 70 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 32. “Interrupts (Part III)” (DS70214) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS70283K-page 72 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vecto
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IRQ) Number IVT Address AIVT Address 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22-23 24 25 26 27 28 29 30 31 32-36 37 38-64 65 66 67-70 71 72 73 74-80 81 82 83-125 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-15 16 17 18 19 20 21 22 23 24-28 29 30-56 57 58 59-62 63 64 65 66-72 73 74 75-117 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002C 0x00
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 7.3 Interrupt Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 7.3.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) IPL2 R/W-0(3) (2) (2) IPL1 R/W-0(3) (2) IPL0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknow
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector tabl
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70283K-page 80 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IF — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IF IC7IF — INT1IF CNIF — MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrup
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 FLTA1IF — — — — QEIIF PWM1IF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 FLTA1IF: PWM1 Fault A Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Int
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — FLTA2IF PWM2IF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 FLTA2IF: PWM2 Fault A Interrupt Flag Status bit 1 =
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-10: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IE — — — — — bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IE IC7IE — INT1IE CNIE — MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Inte
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 FLTA1IE — — — — QEIIE PWM1IE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — FLA2IE PWM2IE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 FLA2IE: PWM2 Fault A Interrupt Enable bit 1 = In
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-13: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Prior
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-14: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC2IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 1
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-15: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 — R/W-0 R/W-0 U1RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Int
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 AD1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: ADC1 Conversion Complete Interrupt P
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-17: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-18: U-0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 R/W-1 — R/W-0 R/W-0 IC8IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 IC7IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Inte
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 INT2IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Int
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-20: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 QEIIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 PWM1IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 10-8 QEIIP<2:0>: QEI Interrupt Priority bits 111
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-21: U-0 IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 R/W-1 — R/W-0 R/W-0 FLTA1IP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits 111
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-23: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 FLTA2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 PWM2IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 8-10 FLTA2IP<2:0>: PWM2 Fault A Interrupt Prior
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 7-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Pr
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 7.5 Interrupt Setup Procedures 7.5.1 INITIALIZATION To configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.0 OSCILLATOR CONFIGURATION The oscillator system for dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices provides: Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.1 CPU Clocking System The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices provide seven system clock options: • • • • • • • Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Secondary (LP) Oscillator Low-Power RC (LPRC) Oscillator FRC Oscillator with postscaler 8.1.1 8.1.1.1 SYSTEM CLOCK SOURCES Fast RC The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.37 MHz.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 For a primary oscillator or FRC oscillator, output ‘FIN’, the PLL output ‘FOSC’ is given by: EQUATION 8-2: • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz ranged needed. • If PLLPOST<1:0> = 0, then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.2 Oscillator Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 8.2.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0>
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 8-2: R/W-0 ROI bit 15 CLKDIV: CLOCK DIVISOR REGISTER(2) R/W-0 R/W-1 DOZE<2:0> Legend: R = Readable bit -n = Value at POR bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 bit 4-0 Note 1: 2: R/W-0 DOZEN(1) R/W-0 R/W-0 FRCDIV<2:0> R/W-0 bit 8 R/W-0 R/W-1 PLLPOST<1:0> bit 7 bit 15 R/W-1 U-0 — R/W-0 R/W-0 R/W-0 PLLPRE<4:0> R/W-0 R/W-0 bit 0 y = Value set from Configuration bits on POR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bi
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center freq
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 8.4 Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices have a safeguard lock built into the switch process. Note: 8.4.1 Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD<1:0> Configuration bits.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 9.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 9.5 Power-Saving Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 9.5.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 9.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 IC8MD IC7MD — — — — IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 IC8MD: Input Capture 8 Module Disable bit 1 = Input Capture 8 m
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — — PWM2MD — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4 PWM2MD: PWM2 Module Disable bit 1 = PWM2 module is disa
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “I/O Ports” (DS70193) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available on Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.2 Open-Drain Configuration In addition to the PORT, LAT and TRIS registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.6 Peripheral Pin Select Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) TABLE 10-1: Function Name Register Configuration Bits INT1 RPINR0 INT1R<4:0> External Interrupt 2 INT2 RPINR1 INT2R<4:0> Timer2 External Clock T2CK RPINR3 T2CKR<4:0> Timer3 External Clock T3CK RPINR3 T3CKR<4:0> IC1 RPINR7 IC1R<4:0> Input Name External Interrupt 1 Input Capture 1 Input Capture 2 IC2 RPINR7 IC2R<4:0> Input Capture 7 IC7 RPINR10 IC7R<4:0> Input Capture 8 IC8 RPINR10
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.6.2.2 Output Mapping FIGURE 10-3: In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.6.3 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dsPIC33F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit pin select lock 10.6.3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.7 1. 2. In some cases, certain pins as defined in TABLE 24-9: “DC Characteristics: I/O Pin Input Specifications” under “Injection Current”, have internal protection diodes to VDD and VSS. The term “Injection Current” is also referred to as “Clamp Current”.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 10.9 Peripheral Pin Select Registers The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices implement 21 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (13) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON[IOLOCK] = 0. See Section 10.6.3.1 “Control Register Lock” for a specific command sequence.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INT2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INT2R<4:0>: Assign External Interrup
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T3CKR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T2CKR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR<4:0>: Assign Timer3 E
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC2R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC2R<4:0>: Assign Input Captu
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC8R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC7R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC8R<4:0>: Assign Input Cap
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OCFAR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Capture
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-8: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTA2R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 FLTA2R<4:0>: Assign PWM2 Fault (F
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-9: RPINR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 QEB1R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 QEA1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 QEB1R<4:0>: Assign B (QEB) to the correspond
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-10: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INDX1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INDX1R<4:0>: Assign QEI INDEX (IND
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-11: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR<4:0>: Assign UART1
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-12: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SCK1R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SDI1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 SCK1R<4:0>: Assign SPI1 Cl
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-13: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SS1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R<4:0>: Assign SPI1 Slave Select
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-14: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP1R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP0R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP1R<4:0>: Peripheral Output F
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-16: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP5R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP4R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP5R<4:0>: Peripheral Output F
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-18: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP9R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP8R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP9R<4:0>: Peripheral Output F
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-20: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP13R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP12R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP13R<4:0>: Peripheral Outpu
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-22: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP17R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP16R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP17R<4:0>: Peripheral Outpu
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-24: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP21R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP20R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP21R<4:0>: Peripheral Out
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 10-26: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP25R<4:0> bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP24R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP25R<4:0>: Peripheral Out
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 11.0 TIMER1 Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 11.1 Timer Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 11.1.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 11.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 146 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 12.0 TIMER2/3 FEATURE Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TIMER2/3 (32-BIT) BLOCK DIAGRAM(1) FIGURE 12-1: 1x T2CK Gate Sync 01 TCY 00 TGATE Q 1 Set T3IF Q 0 Equal Prescaler 1, 8, 64, 256 TGATE TCS D CK PR2 PR3 ADC Event Trigger(2) TCKPS<1:0> 2 TON Comparator MSb LSb TMR3 Reset TMR2 Sync 16 Read TMR2 Write TMR2 16 TMR3HLD 16 16 Data Bus<15:0> Note 1: 2: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 12.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 12-2: R/W-0 TON(2) T3CON CONTROL REGISTER U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE(2) R/W-0 R/W-0 TCKPS<1:0>(2) U-0 — U-0 R/W-0 U-0 — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer3 On bit(2) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimp
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 13.0 INPUT CAPTURE 1. Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 13.1 Input Capture Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 13.1.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 13.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 154 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 14.0 OUTPUT COMPARE The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 14.1 Output Compare Modes application must disable the associated timer when writing to the output compare control registers to avoid malfunctions. Configure the Output Compare modes by setting the appropriate Output Compare Mode bits (OCM<2:0>) in the Output Compare Control register (OCxCON<2:0>). Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 14.2 Output Compare Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 14.2.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 14.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 15.0 MOTOR CONTROL PWM MODULE Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Motor Control PWM” (DS70187) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 15-1: 6-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM1) PWM1CON1 PWM Enable and Mode SFRs PWM1CON2 P1DTCON1 Dead-Time Control SFRs P1DTCON2 P1FLTACON Fault Pin Control SFRs P1OVDCON PWM Manual Control SFR PWM Generator 3 16-bit Data Bus P1DC3 Buffer P1DC3 Comparator PWM Generator 2 P1TMR Channel 3 Dead-Time Generator and Override Logic PWM1H3 Channel 2 Dead-Time Generator and Override Logic PWM1H2 PWM1L3 Output PWM1L2 Driver Comparator PWM Genera
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 15-2: 2-CHANNEL PWM MODULE BLOCK DIAGRAM (PWM2) PWM2CON1 PWM Enable and Mode SFRs PWM2CON2 P2DTCON1 Dead-Time Control SFRs P2DTCON2 P2FLTACON Fault Pin Control SFRs P2OVDCON PWM Manual Control SFR PWM Generator 1 16-bit Data Bus P2DC1Buffer P2DC1 Comparator PWM2H1 Channel 1 Dead-Time Generator and Override Logic PWM2L1 P2TMR Output Driver Comparator Block P2TPER P2TPER Buffer FLTA2 P2TCON Comparator SEVTDIR P2SECMP Special Event Postsca
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 15.3 Motor Control Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 15.3.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 15.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-2: R-0 PxTMR: PWM TIMER COUNT VALUE REGISTER R/W-0 R/W-0 R/W-0 PTDIR R/W-0 R/W-0 R/W-0 R/W-0 PTMR<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTDIR: PWM Time Base Count Direction Status bit (read-only) 1 = PWM time base is c
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-4: R/W-0 PxSECMP: SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 SEVTDIR(1) R/W-0 SEVTCMP<14:8> R/W-0 R/W-0 R/W-0 (2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP<7:0> R/W-0 R/W-0 R/W-0 (2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SEVTDIR: Special Event Trigger Time Base Direction bit(1)
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1(2) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PMOD3 PMOD2 PMOD1 bit 15 bit 8 U-0 R/W-1 R/W-1 R/W-1 — PEN3H(1) PEN2H(1) PEN1H(1) U-0 R/W-1 R/W-1 R/W-1 — PEN3L(1) PEN2L(1) PEN1L(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-6: PWMxCON2: PWM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 SEVOPS<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — IUE OSYNC UDIS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SEVOPS<3:0>: PWM Special Event
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-7: R/W-0 PxDTCON1: DEAD-TIME CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 DTBPS<1:0> R/W-0 R/W-0 R/W-0 R/W-0 DTB<5:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 DTAPS<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTA<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 DTBPS<1:0>: Dead-Time Unit B Prescale Select bits 11 = Clock
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-8: PxDTCON2: DEAD-TIME CONTROL REGISTER 2(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DTS3A DTS3I DTS2A DTS2I DTS1A DTS1I bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 DTS3A: Dead-Time Select for PWM3 S
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-9: PxFLTACON: FAULT A CONTROL REGISTER(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 FLTAM — — — — FAEN3 FAEN2 FAEN1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read a
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-10: PxOVDCON: OVERRIDE CONTROL REGISTER(1) U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unim
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 15-11: PxDC1: PWM DUTY CYCLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDC1<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDC1<15:0>: PWM Duty Cycle 1 Value bits REGISTER 15-12: P1DC2: PWM DUTY CYCLE REGISTER 2
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 16.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE This section describes the Quadrature Encoder Interface (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 16.1 Ouadrature Encoder Interface Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 16.1.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER R/W-0 U-0 R/W-0 R-0 R/W-0 CNTERR — QEISIDL INDEX UPDN R/W-0 R/W-0 R/W-0 QEIM<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE R/W-0 R/W-0 TQCKPS<1:0> R/W-0 R/W-0 R/W-0 POSRES TQCS UPDN_SRC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CNTERR: Count E
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 16-1: QEIxCON: QEI CONTROL REGISTER (CONTINUED) bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (Prescaler utilized for 16-bit Timer mode only) bit 2 POSRES: Position Counter Reset Enable bit 1 = Index Pulse resets Position Counter 0 = Index Pulse does not reset Position Counter Note: Bit applies only when QEIM<2:0> = 100 or 110.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 16-2: DFLTxCON: DIGITAL FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 IMV<1:0> CEID bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 QEOUT QECK<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 IMV<1:0>: Index Match Value bits
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 178 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 17.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18. “Serial Peripheral Interface (SPI)” (DS70206) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip website (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 17.1 1. In Frame mode, if there is a possibility that the master may not be initialized before the slave: a) If FRMPOL (SPIxCON2<13>) = 1, use a pull-down resistor on SSx. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: 2. 5.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 17.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 17-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 SSEN(2) CKP R/W-0 R/W-0 MSTEN R/W-0 R/W-0 R/W-0 SPRE<2:0>(3) R/W-0 PPRE<1:0>(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 17-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: The CKE bit is not used in the Framed SPI modes.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 17-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 18.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit™ (DS70195) of the (I2C™)” “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 18-1: I2C™ BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS70283K-page 18
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 18.2 I2C Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 18.2.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 18.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 18-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ C = Clear only bit R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared -n = Value at POR
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 18-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 18-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “UART” (DS70188) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 19.1 1. 2. UART Helpful Tips In multi-node direct-connect UART networks, UART receive inputs react to the complementary logic level defined by the URXINV bit (UxMODE<4>), which defines the idle state, the default of which is logic high, (i.e., URXINV = 0).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 19.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 19-2: R/W-0 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 UTXISEL1 UTXINV R/W-0 UTXISEL0 U-0 — R/W-0 HC UTXBRK R/W-0 UTXEN (1) R-0 R-1 UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0> R/W-0 R-1 R-0 R-0 R/C-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware cleared C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 20.0 10-BIT/12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip website (www.microchip.com).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 20-1: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ16MC304 AND dsPIC33FJ32MC204 DEVICES AN0 AN8 S/H0 CHANNEL SCAN + CH0SA<4:0> CH0 CH0SB<4:0> - CSCNA AN1 VREFL CH0NA CH0NB AN0 (1) AN3 S/H1 VREF+(1) AVDD VREF- AVSS + - CH123SA CH123SB CH1(2) AN6 VCFG<2:0> ADC1BUF0 VREFL ADC1BUF1 ADC1BUF2 VREFH VREFL CH123NA CH123NB SAR ADC AN1 AN4 CH2(2) S/H2 CH123SA CH123SB + ADC1BUFE - ADC1BUFF AN7 VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123S
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 20-2: ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32MC202 DEVICE AN0 AN5 CHANNEL SCAN CH0SA<4:0> CH0 S/H0 + CH0SB<4:0> - CSCNA AN1 VREFL CH0NA CH0NB AN0 VREF+(1) AVDD VREF-(1) AVSS AN3 S/H1 + - CH123SA CH123SB CH1(2) VCFG<2:0> ADC1BUF0 VREFL ADC1BUF1 ADC1BUF2 VREFH CH123NA CH123NB VREFL SAR ADC AN1 AN4 S/H2 CH123SA CH123SB CH2 + ADC1BUFE - ADC1BUFF (2) VREFL CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - VREFL CH123NA CH123NB
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 20-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3<15> ADC Internal RC Clock(2) 0 TAD AD1CON3<5:0> 1 6 TOSC(1) X2 TCY ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 64 Note 1: 2: 20.3 1. 2. 3. 4. Refer to Figure 8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock frequency. TOSC = 1/FOSC. See the ADC Electrical Characteristics for the exact RC clock value.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 20.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 20-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED) bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion. SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = ADC sample-and-hold amplifiers are sampling 0 = ADC sample-and-hold amplifiers are holding If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 20-2: R/W-0 AD1CON2: ADC1 CONTROL REGISTER 2 R/W-0 R/W-0 VCFG<2:0> U-0 U-0 R/W-0 — — CSCNA R/W-0 R/W-0 CHPS<1:0> bit 15 bit 8 R-0 U-0 BUFS — R/W-0 R/W-0 R/W-0 R/W-0 SMPI<3:0> R/W-0 R/W-0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Converter Voltage Reference Configuration
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 20-3: R/W-0 AD1CON3: ADC1 CONTROL REGISTER 3 U-0 ADRC — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMC<4:0>(1) — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bi
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 20-4: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NB<1:0> R/W-0 CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NA<1:0> R/W-0 CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Ch
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 20-4: bit 2-1 AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER (CONTINUED) CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits dsPIC33FJ32MC202 devices only: If AD12B = 1: 11 = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = 0: 11 = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input is VREF00 = CH1, CH2, CH3 negative input is VREFdsPIC33FJ32MC204 and dsPIC33FJ16MC304 devices only: If AD12B = 1: 11 = Reserved 10 =
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 REGISTER 20-5: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB<4:0> bit 15 bit 8 R/W-0 U-0 U-0 CH0NA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit 1 = Channel 0 negativ
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 ,2 REGISTER 20-6: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CSS8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 CSS<8:0>: A
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.0 SPECIAL FEATURES Note: 21.1 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices provide nonvolatile memory implementation for device configuration bits. Refer to Section 25. “Device Configuration” (DS70194) of the “dsPIC33F/PIC24H Family Reference Manual”, for more information on this implementation. This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 21-2: CONFIGURATION BITS DESCRIPTION RTSP Effect Bit Field Register Description BWRP FBS Immediate Boot Segment Program Flash Write Protection 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate dsPIC33FJ32MC202 and dsPIC33FJ32MC204 Devices Only Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 768 Instruction Words (except interrupt vectors) 110 = Standard securit
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 21-2: CONFIGURATION BITS DESCRIPTION (CONTINUED) RTSP Effect Bit Field Register FCKSM<1:0> FOSC Immediate Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY FOSC Immediate Peripheral pin select configuration 1 = Allow only one reconfiguration 0 = Allow multiple rec
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 21-2: CONFIGURATION BITS DESCRIPTION (CONTINUED) RTSP Effect Bit Field Register HPOL FPOR Immediate Motor Control PWM High Side Polarity bit 1 = PWM module high side output pins have active-high output polarity 0 = PWM module high side output pins have active-low output polarity LPOL FPOR Immediate Motor Control PWM Low Side Polarity bit 1 = PWM module low side output pins have active-high output polarity 0 = PWM module low side output pins have activ
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.2 On-Chip Voltage Regulator The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family incorporate an on-chip regulator that allows the device to run its core logic from VDD.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.4 Watchdog Timer (WDT) 21.4.2 For dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 21.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.5 JTAG Interface 21.7 In-Circuit Debugger dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface will be provided in future revisions of the document. When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 21.8 Code Protection and CodeGuard™ Security The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices offer the intermediate implementation of CodeGuard™ Security. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. This feature helps protect individual Intellectual Property in collaborative system designs.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 22.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0...
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: Base Instr # 1 2 3 4 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z OA,
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: Base Instr # 9 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTG BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3)
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 22-2: Base Instr # 66 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC SAC Assembly Syntax # of # of Words Cycles Description Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 23.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 23.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 23.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 23.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 23.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 24.1 DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temp Range (in °C) — VBOR-3.6V(1) -40°C to +85°C 40 — VBOR-3.6V(1) -40°C to +125°C 40 Note 1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units 3.0 — 3.6 V Conditions Operating Voltage DC10 Supply Voltage VDD — (2) Industrial and Extended DC12 VDR RAM Data Retention Voltage 1.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage DI10 I/O pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param Symbol No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: 2x Sink Driver Pins - All pins not defined by 4x or 8x driver pins — — 0.4 V IOL ≤3 mA, VDD = 3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended DC CHARACTERISTICS Param No. BO10 Note 1: 2: Characteristic(1) Symbol Min Typ Max Units Conditions BOR Event on VDD transition 2.40 — 2.55 V See Note 2 VBOR Parameters are for design guidance only and are not tested in manufacturing.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Param No. — Note 1: Symbol Characteristics CEFC Min External Filter Capacitor 4.7 Value(1) Typical VCAP voltage = 2.5V when VDD ≥ VDDMIN. © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 24.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 AC characteristics and timing parameters. TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Operating voltage VDD range as described in Table 24-1.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 OS30 OS30 Q3 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 24-1 for load conditions. TABLE 24-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out OSC Time-out SY11 SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-1 for load conditions. DS70283K-page 248 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 24-1 for load conditions. TABLE 24-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-6: TIMERQ (QEI MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEB TQ11 TQ10 TQ15 TQ20 POSCNT TABLE 24-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 24-1 for load conditions. TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-9: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 Active OCx Tri-state TABLE 24-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-10: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTA MP20 PWMx FIGURE 24-11: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 24-1 for load conditions. TABLE 24-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-12: QEA/QEB INPUT CHARACTERISTICS TQ36 QEA (input) TQ30 TQ31 TQ35 QEB (input) TQ41 TQ40 TQ30 TQ31 TQ35 QEB Internal TABLE 24-30: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-13: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset TABLE 24-31: QEI INDEX PULSE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-32: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-15: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx LSb SP30, SP31 Note: Refer to Figure 24-1 for load conditions. TABLE 24-33: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-16: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 24-1 for load conditions. TABLE 24-34: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-17: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP30, SP31 SDIx MSb In LSb SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 24-1 for load conditions. TABLE 24-35: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70283K-page 262 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-19: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70283K-page 264 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-20: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70283K-page 266 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-38: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-21: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70283K-page 268 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-39: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-22: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 24-1 for load conditions. FIGURE 24-23: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 24-1 for load conditions. DS70283K-page 270 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-40: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-24: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 24-25: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70283K-page 272 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-41: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-42: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param Symb No. ol Characteristic Min. Typ Max. Units Lesser of VDD + 0.3 or 3.6 V VSS + 0.3 V Conditions Device Supply AD01 AD02 AVDD AVSS Module VDD Supply(2) Module VSS Supply(2) Greater of VDD – 0.3 or 3.0 — VSS – 0.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-43: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-44: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF-(3) AD20b Nr Resolution(4) AD21b INL Integral Nonlinearity -1.5 — +1.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-26: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 9 1 – Software sets AD1CON. SAMP to start sampling. 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 24-27: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 AD55 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 5 6 7 1 – Software sets AD1CON. SAMP to start sampling. 5 – Convert bit 9. 2 – Sampling starts after discharge period. TSAMP is described in Section 16.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 24-46: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V AC CHARACTERISTICS Param Symbol No. (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic Min. Typ(1) Max.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 280 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 25.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. The specifications between -40°C to +150°C are identical to those shown in Section 24.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 25.1 High Temperature DC Characteristics TABLE 25-1: OPERATING MIPS VS. VOLTAGE Characteristic VDD Range (in Volts) Temperature Range (in °C) HDC5 VBOR to 3.6V(1) -40°C to +150°C Note 1: Max MIPS dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 20 Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Power-Down Current (IPD) HDC60e 250 2000 μA +150°C 3.3V Base Power-Down Current(1,3) HDC61c 3 5 μA +150°C 3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-7: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: 2x Sink Driver Pins - All pins not defined by 4x or 8x driver pins — — 0.4 V IOL ≤1.8 mA, VDD = 3.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 25.2 AC Characteristics and Timing Parameters Parameters in this section begin with an H, which denotes High temperature. For example, parameter OS53 in Section 24.2 “AC Characteristics and Timing Parameters” is the Industrial and Extended temperature equivalent of HOS53. The information contained in this section defines dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 AC characteristics and timing parameters for high temperature devices.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-10: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-15: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature Characteristic Min Typ Max Units 600 50 μA μA Conditions Reference Inputs HAD08 Note 1: 2: IREF Current Drain — — 250 — ADC operating, See Note 1 ADC off, See Note 1 These parameters are not characterized or tested in manufacturing.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-17: ADC MODULE SPECIFICATIONS (10-BIT MODE)(3) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 25-18: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No.
DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 26-1: VOH – 2x DRIVER PINS -0.040 -0.016 -0.035 3.
FIGURE 26-7: VOL – 2x DRIVER PINS 0.060 0.020 0.018 3.6V 0.016 3.6V 0.050 3.3V 3.3V 0.014 0.040 3V 0.012 IOL (A) IOL (A) VOL – 8x DRIVER PINS 0.010 0.008 3V 0.030 0.020 0.006 0.004 0.010 0.002 0.000 0.00 1.00 2.00 3.00 0.000 0.00 4.00 1.00 FIGURE 26-6: VOL – 4x DRIVER PINS FIGURE 26-8: 3.00 4.00 VOL – 16x DRIVER PINS 0.120 0.040 0.035 3.6V 0.030 3.6V 0.100 3.3V 0.025 3.3V 0.080 3V IOL (A) © 2007-2012 Microchip Technology Inc. IOL (A) 2.00 VOL (V) VOL (V) 0.
TYPICAL IPD CURRENT @ VDD = 3.3V, +85ºC FIGURE 26-11: 700 60.00 600 50.00 500 Current (mA) IPD Current [µA] TYPICAL IDOZE CURRENT @ VDD = 3.3V, +85ºC 400 300 40.00 30.00 20.00 200 10.00 100 0 0.00 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Celsius TYPICAL IDD CURRENT @ VDD = 3.3V, +85ºC FIGURE 26-10: 1:2 1:64 1:128 Doze Ratio FIGURE 26-12: TYPICAL IIDLE CURRENT @ VDD = 3.
TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 26-14: 35 7450 33 7400 LPRC Frequency (kHz) L 31 7350 Frequen ncy (kHz) TYPICAL LPRC FREQUENCY @ VDD = 3.3V 7300 7250 7200 29 27 25 23 21 19 7150 7100 17 15 -40 -30 -20 -10 0 10 20 30 40 50 60 70 Temperature Celsius 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 Temperature Celsius 80 90 100 110 120 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 28-Lead SPDIP Example dsPIC33FJ32MC 202-E/SP e3 0730235 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 27.1 Package Marking Information (Continued) 28-Lead QFN-S Example XXXXXXXX XXXXXXXX YYWWNNN 44-Lead QFN 33FJ32MC 202E/MM e3 0730235 Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 27.2 Package Details 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 298 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 300 © 2007-2012 Microchip Technology Inc.
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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 302 © 2007-2012 Microchip Technology Inc.
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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS70283K-page 306 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A – 0.80 BSC – Molded Package Thickness A2 0.95 1.00 1.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 308 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 APPENDIX A: REVISION HISTORY Revision A (February 2007) This is the initial released version of the document. Revision B (May 2007) This revision includes the following corrections and updates: • Minor typographical and formatting corrections throughout the data sheet text. • New content: - Addition of bullet item (16-word conversion result buffer) (see Section 20.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision C (June 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name “High-Performance, 16-bit Digital Signal Controllers” Update Description Added Extended Interrupts column to Remappable Peripherals in the Controller Families table and Note 3 (see Table 1).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 15.0 “Motor Control PWM Module” Update Description Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • • • • • • • • • • • • • • • • Section 16.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 18.0 “Inter-Integrated Circuit™ (I2C™)” Update Description Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • • • • • • • • • • • • 17.3 “I2C Interrupts” 17.4 “Baud Rate Generator” (retained Figure 15-1: I2C Block Diagram) 17.5 “I2C Module Addresses” 17.6 “Slave Address Masking” 17.7 “IPMI Support” 17.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 21.0 “Special Features” Update Description Added FICD register information for address 0xF8000E in the Device Configuration Register Map (see Table 21-1). Added FICD register content (BKBUG, COE, JTAGEN, and ICS<1:0> to the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Configuration Bits Description (see Table 21-2).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision D (December 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Controllers” Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Diagrams”). Section 2.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision E (June 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2 or 3) to PGECx and PGEDx Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE All other major changes are referenced by their respective section in the following table.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision F (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision H (February 2011) This revision includes typographical and formatting changes throughout the data sheet text. In addition, all instances of VDDCORE have been removed. All other major changes are referenced by their respective section in the following table.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-6: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 24.0 “Electrical Characteristics” Update Description Added the 28-pin SSOP Thermal Packaging Characteristics (see Table 24-3). Removed Note 4 from the DC Temperature and Voltage Specifications (see Table 24-4). Updated the maximum value for parameter DI19 and added parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input Specifications (see Table 24-9).
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision J (July 2011) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-7: MAJOR SECTION UPDATES Section Name Update Description Section 21.0 “Special Features” Added Note 3 to the Connections for the On-chip Voltage Regulator diagram (see Figure 21-1). Section 24.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 320 © 2007-2012 Microchip Technology Inc.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INDEX A AC Characteristics .................................................... 244, 285 ADC Module.............................................................. 288 ADC Module (10-bit Mode) ....................................... 289 ADC Module (12-bit Mode) ....................................... 288 Internal RC Accuracy ................................................ 246 Load Conditions ................................................
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 H High Temperature Electrical Characteristics..................... 281 I I/O Ports ............................................................................ 117 Parallel I/O (PIO)....................................................... 117 Write/Read Timing .................................................... 118 I2 C Addresses ................................................................. 187 Operating Modes ...................................................
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 AD1CSSL (ADC1 Input Scan Select Low)................ 210 AD1PCFGL (ADC1 Port Configuration Low) ............ 210 CLKDIV (Clock Divisor)............................................. 107 CORCON (Core Control) ...................................... 23, 75 DFLTCON (QEI Control)........................................... 177 I2CxCON (I2Cx Control) ........................................... 188 I2CxMSK (I2Cx Slave Mode Address Mask) ............
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 SPIx Module Slave Mode (CKE = 1)......................... 287 Timing Specifications 10-bit ADC Conversion Requirements ...................... 279 12-bit ADC Conversion Requirements ...................... 277 I2Cx Bus Data Requirements (Master Mode) ........... 271 I2Cx Bus Data Requirements (Slave Mode) ............. 273 Motor Control PWM Requirements ........................... 255 Output Compare Requirements ................................ 253 PLL Clock..........
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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 MC2 02 T E / SP - XXX Examples: a) Microchip Trademark Architecture dsPIC33FJ32MC202TE/SP: Motor Control dsPIC33, 32 KB program memory, 28-pin, Extended temp., SPDIP package.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 328 © 2007-2012 Microchip Technology Inc.
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