Datasheet

© 2007-2012 Microchip Technology Inc. DS70283K-page 67
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
6.4 Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
V
DD crosses the VPOR threshold and the delay TPOR
has elapsed. The delay TPOR ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 24.0 “Electrical Characteristics” for details.
The POR status bit (POR) in the Reset Control register
(RCON<0>) is set to indicate the Power-on Reset.
6.4.1 Brown-out Reset (BOR) and
Power-up timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(V
DD < VBOR) for proper device operation. The BOR
circuit keeps the device in Reset until VDD crosses
VBOR threshold and the delay TBOR has elapsed. The
delay T
BOR ensures the voltage regulator output
becomes stable.
The BOR status bit (BOR) in the Reset Control register
(RCON<1>) is set to indicate the Brown-out Reset.
The device will not run at full speed after a BOR as the
V
DD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST
is released.
The power-up timer delay (T
PWRT) is programmed by
the Power-on Reset Timer Value Select bits
(FPWRT<2:0>) in the POR Configuration register
(FPOR<2:0>), which provides eight settings (from 0 ms
to 128 ms). Refer to Section 21.0 “Special Features”
for further details.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (T
BOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point
TABLE 6-2: OSCILLATOR DELAY
Symbol Parameter Value
VPOR POR threshold 1.8V nominal
T
POR POR extension time 30 μs maximum
V
BOR BOR threshold 2.5V nominal
T
BOR BOR extension time 100 μs maximum
T
PWRT Programmable power-up time delay 0-128 ms nominal
TFSCM Fail-Safe Clock Monitor Delay 900 μs maximum
Note: When the device exits the Reset
condition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, other-
wise the device may not function cor-
rectly. The user application must
ensure that the delay between the time
power is first applied, and the time
SYSRST
becomes inactive, is long
enough to get all operating parameters
within specification.