Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 347
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FWDTEN FWDT Immediate
Watchdog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC oscillator cannot be
disabled; clearing the SWDTEN bit in the RCON register will
have no effect)
0 = Watchdog Timer is enabled/disabled by user software (LPRC can
be disabled by clearing the SWDTEN bit in the RCON register)
WINDIS FWDT Immediate Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
WDTPRE FWDT Immediate Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST<3:0> FWDT Immediate Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
FPWRT<2:0> FPOR Immediate Power-on Reset Timer Value Select bits
111 = PWRT = 128 ms
110 = PWRT = 64 ms
101 = PWRT = 32 ms
100 = PWRT = 16 ms
011 = PWRT = 8 ms
010 = PWRT = 4 ms
001 = PWRT = 2 ms
000 = PWRT = Disabled
JTAGEN FICD Immediate JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS<1:0> FICD Immediate ICD Communication Channel Select Enable bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
ALTQIO FPOR Immediate Enable Alternate QEI1 Pin bit
1 = QEA1, QEB1 and INDX1 are selected as inputs to QEI1
0 = AQEA1, AQEB1 and AINDX1 are selected as inputs to QEI1
ALTSS1 FPOR Immediate
Enable Alternate SS1
pin bit
1 = ASS1
is selected as the I/O pin for SPI1
0 = SS1
is selected as the I/O pin for SPI1
CMPPOL0 FCMP Immediate Comparator Hysteresis Polarity bit (for even numbered comparators)
1 = Hysteresis is applied to falling edge
0 = Hysteresis is applied to rising edge
HYST0<1:0> FCMP Immediate Comparator Hysteresis Select bits
11 = 45 mV hysteresis
10 = 30 mV hysteresis
01 = 15 mV hysteresis
00 = No hysteresis
TABLE 24-2: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field Register RTSP Effect Description