Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70591E-page 320  2009-2012 Microchip Technology Inc.
REGISTER 22-6: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IRQEN0 PEND0 SWTRG0
TRGSRC0<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 IRQEN1: Interrupt Request Enable 1 bit
1 = Enables IRQ generation when requested conversion of Channels AN3 and AN2 is completed
0 = IRQ is not generated
bit 14 PEND1: Pending Conversion Status 1 bit
1 = Conversion of Channels AN3 and AN2 is pending; set when selected trigger is asserted
0 = Conversion is complete
bit 13 SWTRG1: Software Trigger 1 bit
1 = Starts conversion of AN3 and AN2 (if selected in the TRGSRC bits)
(1)
This bit is automatically cleared by hardware when the PEND1 bit is set.
0 = Conversion has not started
Note 1: The trigger source must be set as a global software trigger prior to setting this bit to ‘1’. If other
conversions are in progress, the conversion is performed when the conversion resources are available.