Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 262  2009-2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

SPIEN

— SPISIDL — — — — —

bit 15 bit 8

U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0

— SPIROV — — — — SPITBF SPIRBF

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 SPIEN: SPIx Enable bit

1 = Enables module and configures SCKx, SDOx, SDIx and SSx

as serial port pins

0 = Disables module

bit 14 Unimplemented: Read as ‘0’

bit 13 SPISIDL: SPIx Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 SPIROV: SPIx Receive Overflow Flag bit

1 = A new byte/word is completely received and discarded; the user software has not read the

previous data in the SPIxBUF register

0 = No overflow has occurred

bit 5-2 Unimplemented: Read as ‘0’

bit 1 SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit has not yet started, SPIxTXB is full

0 = Transmit has started, SPIxTXB is empty. Automatically set in hardware when CPU writes the

SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module

transfers data from SPIxTXB to SPIxSR.

bit 0 SPIRBF: SPIx Receive Buffer Full Status bit

1 = Receive is complete, SPIxRXB is full

0 = Receive is not complete, SPIxRXB is empty. Automatically set in hardware when SPIx transfers

data from SPIxSR to SPIxRXB. Automatically cleared in hardware when the core reads the

SPIxBUF location, reading SPIxRXB.