Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70591E-page 26  2009-2012 Microchip Technology Inc.
2.7 Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < F
IN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV, and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8 Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the
Analog-to-Digital input pins (ANx) as “digital” pins, by
setting all bits in the ADPCFG and ADPCFG2 registers.
The bits in the registers that correspond to the
analog-to-digital pins that are initialized by MPLAB ICD 2,
ICD 3, or REAL ICE, must not be cleared by the user
application firmware; otherwise, communication errors
will result between the debugger and the device.
If your application needs to use certain analog-to-digital
pins as analog input pins during the debug session, the
user application must clear the corresponding bits in
the ADPCFG and ADPCFG2 registers during
initialization of the ADC module.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the ADPCFG and ADPCFG2
registers. Automatic initialization of these registers is
only done during debugger operation. Failure to
correctly configure the register(s) will result in all
analog-to-digital pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.9 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between V
SS
and unused pins and drive the output to logic low.
2.10 Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-11.