Datasheet

 2009-2012 Microchip Technology Inc. DS70591E-page 259
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
bit 5 TQGATE: Timer Gated Time Accumulation Enable bit
1 = Timer gated time accumulation is enabled
0 = Timer gated time accumulation is disabled
bit 4-3 TQCKPS<1:0>: Timer Input Clock Prescale Select bits
(3)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 2 POSRES: Position Counter Reset Enable bit
(4)
1 = Index pulse resets position counter
0 = Index pulse does not reset position counter
bit 1 TQCS: Timer Clock Source Select bit
1 = External clock from pin, QEAx (on the rising edge)
0 = Internal clock (T
CY)
bit 0 UPDN_SRC: Position Counter Direction Selection Control bit
(5)
1 = QEBx pin state defines the position counter direction
0 = Control/status bit, UPDN (QEIxCON<11>), defines the timer counter (POSxCNT) direction
REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) (CONTINUED)
Note 1: CNTERR flag only applies when QEIM<2:0> = 110 or 100.
2: Read-only bit when QEIM<2:0> = 1xx. Read/write bit when QEIM<2:0> = 001.
3: Prescaler utilized for 16-Bit Timer mode only.
4: This bit applies only when QEIM<2:0> = 100 or 110.
5: When configured for QEI mode, this control bit is a ‘don’t care’.