Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70591E-page 188  2009-2012 Microchip Technology Inc.
FIGURE 9-1: OSCILLATOR SYSTEM DIAGRAM
÷ N
ACLK
SELACLK APSTSCLR<2:0>
To PW M / A D C
(1)
ENAPLLASRCSEL FRCSEL
POSCCLK
FRCCLK
÷ N
ROSEL RODIV<3:0>
REFCLKO
(3)
POSCCLK
Reference Clock Generation
Auxiliary Clock Generation
Note 1: See Section 9.1.3 “PLL Configuration” and Section 9.2 “Auxiliary Clock Generation” for configuration restrictions.
2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected.
3: REFCLKO functionality is not available if the primary oscillator is used.
4: The term, F
P, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this
document, F
P and FCY are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode
is used in any ratio other than 1:1, which is the default.
F
VCO
(1)
FOSC
Secondary Oscillator (SOSC)
LPOSCEN
SOSCO
SOSCI
Timer 1
OSC2
OSC1
Primary Oscillator (POSC)
XTPLL, HSPLL,
XT, HS, EC
FRCDIV<2:0>
WDT, PWRT,
FSCM
FRCDIVN
SOSC
FRCDIV16
ECPLL, FRCPLL
NOSC<2:0> FNOSC<2:0>
Reset
FRC
Oscillator
LPRC
Oscillator
DOZE<2:0>
S3
S1
S2
S1/S3
S7
S6
FRC
LPRC
S0
S5
S4
÷ 16
Clock Switch
S7
Clock Fail
÷ 2
TUN<5:0>
PLL
(1)
F CY
(4)
F OSC
FRCDIV
DOZE
FVCO
(1)
To AD C a n d
Generator
R
(2)
POSCMD<1:0>
POSCCLK
F P
(4)
Auxiliary Clock
APLL
(1)
x16