Datasheet

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS70591E-page 158  2009-2012 Microchip Technology Inc.
REGISTER 7-29: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— C1IP<2:0>
(1)
— C1RXIP<2:0>
(1)
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— SPI2IP<2:0> — SPI2EIP<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits
(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits
(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
Note 1: Interrupts are disabled on devices without ECAN™ modules.