Datasheet

© 2007-2011 Microchip Technology Inc. DS70290J-page 293
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
OSCTUN (FRC Oscillator Tuning) ............................ 106
PLLFBD (PLL Feedback Divisor).............................. 105
PMD1 (Peripheral Module Disable Control
Register 1) ........................................................ 112
PMD2 (Peripheral Module Disable Control
Register 2) ........................................................ 113
RCON (Reset Control) ................................................ 63
SPIxCON1 (SPIx Control 1)...................................... 158
SPIxCON2 (SPIx Control 2)...................................... 160
SPIxSTAT (SPIx Status and Control) ....................... 157
SR (CPU Status)................................................... 21, 75
T1CON (Timer1 Control)........................................... 139
TxCON (T2CON, T4CON, T6CON or
T8CON Control)................................................ 144
TyCON (T3CON, T5CON, T7CON or
T9CON Control)................................................ 145
UxMODE (UARTx Mode).......................................... 171
UxSTA (UARTx Status and Control)......................... 173
Reset
Illegal Opcode ....................................................... 61, 69
Trap Conflict.......................................................... 68, 69
Uninitialized W Register........................................ 61, 69
Reset Sequence ................................................................. 71
Resets................................................................................. 61
S
Serial Peripheral Interface (SPI) ....................................... 155
Software Reset Instruction (SWR) ...................................... 68
Software Simulator (MPLAB SIM)..................................... 207
Software Stack Pointer, Frame Pointer
CALL Stack Frame...................................................... 45
Special Features of the CPU ............................................ 189
SPI Module
SPI1 Register Map...................................................... 38
Symbols Used in Opcode Descriptions............................. 198
System Control
Register Map............................................................... 44
T
Temperature and Voltage Specifications
AC ..................................................................... 220, 257
Timer1............................................................................... 137
Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ..................... 141
Timing Characteristics
CLKO and I/O ........................................................... 223
Timing Diagrams
10-bit A/D Conversion............................................... 250
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) .................................. 250
12-bit A/D Conversion (ASAM = 0, SSRC = 000) ..... 249
Brown-out Situations................................................... 68
External Clock .......................................................... 221
I2Cx Bus Data (Master Mode) .................................. 242
I2Cx Bus Data (Slave Mode) .................................... 244
I2Cx Bus Start/Stop Bits (Master Mode)................... 242
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 244
Input Capture (CAPx) ............................................... 228
OC/PWM .................................................................. 229
Output Compare (OCx) ............................................ 228
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ......................................... 224
Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 226
Timing Requirements
ADC Conversion (10-bit mode) ................................ 262
ADC Conversion (12-bit Mode) ................................ 262
CLKO and I/O ........................................................... 223
External Clock .......................................................... 221
Input Capture............................................................ 228
SPIx Master Mode (CKE = 0) ................................... 258
SPIx Module Master Mode (CKE = 1) ...................... 258
SPIx Module Slave Mode (CKE = 0) ........................ 259
SPIx Module Slave Mode (CKE = 1) ........................ 259
Timing Specifications
10-bit A/D Conversion Requirements ....................... 251
12-bit A/D Conversion Requirements ....................... 249
I2Cx Bus Data Requirements (Master Mode)........... 243
I2Cx Bus Data Requirements (Slave Mode)............. 245
Output Compare Requirements................................ 228
PLL Clock ......................................................... 222, 257
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out
Reset Requirements......................................... 225
Simple OC/PWM Mode Requirements ..................... 229
Timer1 External Clock Requirements....................... 226
Timer2 External Clock Requirements....................... 227
Timer3 External Clock Requirements....................... 227
U
UART Module
UART1 Register Map ................................................. 38
Using the RCON Status Bits............................................... 69
V
Voltage Regulator (On-Chip) ............................................ 193
W
Watchdog Time-out Reset (WDTR).................................... 68
Watchdog Timer (WDT)............................................ 189, 194
Programming Considerations ................................... 194
WWW Address ................................................................. 295
WWW, On-Line Support ....................................................... 7