Datasheet
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DS70290J-page 292 © 2007-2011 Microchip Technology Inc.
Registers................................................................... 163
I
2
C Module
I2C1 Register Map ...................................................... 38
In-Circuit Debugger ........................................................... 196
In-Circuit Emulation........................................................... 189
In-Circuit Serial Programming (ICSP) ....................... 189, 196
Input Capture
Registers................................................................... 149
Input Change Notification.................................................. 116
Instruction Addressing Modes............................................. 45
File Register Instructions ............................................ 45
Fundamental Modes Supported.................................. 46
MAC Instructions......................................................... 46
MCU Instructions ........................................................ 45
Move and Accumulator Instructions............................ 46
Other Instructions........................................................ 46
Instruction Set
Overview ................................................................... 200
Summary................................................................... 197
Instruction-Based Power-Saving Modes ........................... 109
Idle ............................................................................ 110
Sleep......................................................................... 109
Internal RC Oscillator
Use with WDT ........................................................... 194
Internet Address................................................................ 295
Interrupt Control and Status Registers................................ 74
IECx ............................................................................ 74
IFSx............................................................................. 74
INTCON1 .................................................................... 74
INTCON2 .................................................................... 74
IPCx ............................................................................ 74
Interrupt Setup Procedures ................................................. 96
Initialization ................................................................. 96
Interrupt Disable.......................................................... 96
Interrupt Service Routine ............................................ 96
Trap Service Routine .................................................. 96
Interrupt Vector Table (IVT) ................................................ 71
Interrupts Coincident with Power Save Instructions.......... 110
J
JTAG Boundary Scan Interface ........................................ 189
M
Memory Organization.......................................................... 29
Microchip Internet Web Site .............................................. 295
Modulo Addressing ............................................................. 47
Applicability ................................................................. 48
Operation Example ..................................................... 47
Start and End Address................................................ 47
W Address Register Selection .................................... 47
MPLAB ASM30 Assembler, Linker, Librarian ................... 206
MPLAB Integrated Development Environment Software .. 205
MPLAB PM3 Device Programmer..................................... 208
MPLAB REAL ICE In-Circuit Emulator System................. 207
MPLINK Object Linker/MPLIB Object Librarian ................ 206
N
NVM Module
Register Map............................................................... 44
O
Open-Drain Configuration ................................................. 116
Output Compare................................................................ 151
Registers................................................................... 154
P
Packaging ......................................................................... 267
Details....................................................................... 269
Marking............................................................. 267, 268
Peripheral Module Disable (PMD) .................................... 110
Pinout I/O Descriptions (table)............................................ 11
PMD Module
Register Map .............................................................. 44
PORTA
Register Map .............................................................. 43
PORTB
Register Map .............................................................. 43
Power-on Reset (POR)....................................................... 67
Power-Saving Features .................................................... 109
Clock Frequency and Switching ............................... 109
Program Address Space..................................................... 29
Construction ............................................................... 50
Data Access from Program Memory Using
Program Space Visibility..................................... 53
Data Access from Program Memory Using
Table Instructions ............................................... 52
Data Access from, Address Generation ..................... 51
Memory Map............................................................... 29
Table Read Instructions
TBLRDH ............................................................. 52
TBLRDL.............................................................. 52
Visibility Operation ...................................................... 53
Program Memory
Interrupt Vector........................................................... 30
Organization ............................................................... 30
Reset Vector............................................................... 30
R
Reader Response............................................................. 296
Registers
AD1CHS0 (ADC1 Input Channel 0 Select ................ 185
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 183
AD1CON1 (ADC1 Control 1) .................................... 179
AD1CON2 (ADC1 Control 2) .................................... 181
AD1CON3 (ADC1 Control 3) .................................... 182
AD1CSSL (ADC1 Input Scan Select Low)................ 187
AD1PCFGL (ADC1 Port Configuration Low) ............ 187
CLKDIV (Clock Divisor) ............................................ 103
CORCON (Core Control) ...................................... 23, 75
I2CxCON (I2Cx Control) ........................................... 164
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 168
I2CxSTAT (I2Cx Status) ........................................... 166
ICxCON (Input Capture x Control)............................ 149
IEC0 (Interrupt Enable Control 0) ................... 83, 85, 86
IFS0 (Interrupt Flag Status 0) ..................................... 79
IFS1 (Interrupt Flag Status 1) ..................................... 81
IFS4 (Interrupt Flag Status 4) ..................................... 82
INTCON1 (Interrupt Control 1).................................... 76
INTCON2 (Interrupt Control 2).................................... 78
INTTREG Interrupt Control and Status Register ........ 95
IPC0 (Interrupt Priority Control 0) ............................... 87
IPC1 (Interrupt Priority Control 1) ............................... 88
IPC16 (Interrupt Priority Control 16) ........................... 94
IPC2 (Interrupt Priority Control 2) ............................... 89
IPC3 (Interrupt Priority Control 3) ............................... 90
IPC4 (Interrupt Priority Control 4) ............................... 91
IPC5 (Interrupt Priority Control 5) ............................... 92
IPC7 (Interrupt Priority Control 7) ............................... 93
NVMCOM (Flash Memory Control)....................... 57, 58
OCxCON (Output Compare x Control) ..................... 154
OSCCON (Oscillator Control) ................................... 101