Datasheet

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DS70290J-page 144 © 2007-2011 Microchip Technology Inc.
12.3 Timer2/3 Control Registers
REGISTER 12-1: T2CON CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON
—TSIDL— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
— TGATE TCKPS<1:0> T32 —TCS—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer2 On bit
When T32 =
1:
1 = Starts 32-bit Timer2/3
0 = Stops 32-bit Timer2/3
When T32 =
0:
1 = Starts 16-bit Timer2
0 = Stops 16-bit Timer2
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer2 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS =
0:
1 = Gated time accumulation enabled
0 = Gated time accumulation disabled
bit 5-4 TCKPS<1:0>: Timer2 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-bit Timer Mode Select bit
1 = Timer2 and Timer3 form a single 32-bit timer
0 = Timer2 and Timer3 act as two 16-bit timers
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer2 Clock Source Select bit
1 = External clock from pin T2CK (on the rising edge)
0 = Internal clock (F
CY)
bit 0 Unimplemented: Read as ‘0’