Datasheet

© 2009 Microchip Technology Inc. DS70286C-page 41
dsPIC33FJXXXGPX06/X08/X10
XBREV 0050 BREN XB<14:0> xxxx
DISICNT 0052 — — Disable Interrupts Counter Register xxxx
BSRAM 0750 — — — — — — — — — — — — —
IW_BSR IR_BSR RL_BSR
0000
SSRAM 0752 — — — — — — — — — — — — —
IW_SSR IR_SSR RL_SSR
0000
TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED)
SFR Name
SFR
Addr
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.