Datasheet

© 2009 Microchip Technology Inc. DS70286C-page 177
dsPIC33FJXXXGPX06/X08/X10
17.0 INTER-INTEGRATED
CIRCUIT™ (I
2
C™)
The Inter-Integrated Circuit (I
2
C) module provides
complete hardware support for both Slave and
Multi-Master modes of the I
2
C serial communication
standard, with a 16-bit interface.
The dsPIC33FJXXXGPX06/X08/X10 devices have up
to two I
2
C interface modules, denoted as I2C1 and
I2C2. Each I
2
C module has a 2-pin interface: the SCLx
pin is clock and the SDAx pin is data.
Each I
2
C module ‘x’ (x = 1 or 2) offers the following key
features:
•I
2
C interface supporting both master and slave
operation.
•I
2
C Slave mode supports 7 and 10-bit address.
•I
2
C Master mode supports 7 and 10-bit address.
•I
2
C Port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for I
2
C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
•I
2
C supports multi-master operation; detects bus
collision and will arbitrate accordingly.
17.1 Operating Modes
The hardware fully implements all the master and slave
functions of the I
2
C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
The I
2
C module can operate either as a slave or a
master on an I
2
C bus.
The following types of I
2
C operation are supported:
•I
2
C slave operation with 7-bit address
•I
2
C slave operation with 10-bit address
•I
2
C master operation with 7 or 10-bit address
For details about the communication sequence in each
of these modes, please refer to the “dsPIC33F Family
Reference Manual”.
17.2 I
2
C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-bit Address mode. The
I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
Note: This data sheet summarizes the features
of the dsPIC33FJXXXGPX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 19.
“Inter-Integrated Circuit™ (I
2
C™)”
(DS70195) in the “dsPIC33F Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com).