dsPIC33FJXXXGPX06/X08/X10 Data Sheet High-Performance, 16-Bit Digital Signal Controllers © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
dsPIC33FJXXXGPX06/X08/X10 High-Performance, 16-Bit Digital Signal Controllers Operating Range: Digital I/O: • Up to 40 MIPS operation (at 3.0-3.
dsPIC33FJXXXGPX06/X08/X10 Communication Modules: Analog-to-Digital Converters (ADCs): • 3-wire SPI (up to two modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™ (up to two modules): - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART (up to two modules): - Interrupt on address bit d
dsPIC33FJXXXGPX06/X08/X10 dsPIC33F PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. The dsPIC33F General Purpose Family of devices are ideal for a wide variety of 16-bit MCU embedded applications. The controllers with codec interfaces are well-suited for speech and audio processing applications. Pins Program Flash Memory (Kbyte) RAM (Kbyte)(1) 16-bit Timer Input Capture Output Compare Std.
dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP206 dsPIC33FJ128GP206 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 I
dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP306 dsPIC33FJ128GP306 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CT
dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ256GP506 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/
dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CSDO/RG13 CSDI/RG12 CSCK/RG14 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dsPIC33FJ64GP706 dsPIC33FJ128GP706 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC
dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 80-Pin TQFP IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 64 63 62 61 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 CSCK/RG14 CSDI/RG12 78 77 76 75 74 73 72 71 70 69 68 67 66 65 80 79 CSDO/RG13 = Pins are up to 5V tolerant 1 60 PGEC2/SOSCO/T1CK/CN0/RC14 2 59 PGED2/SOSCI/CN1/RC13 OC1/RD0 AN18/T4CK/T9CK/RC3 3 4 58 57 IC4/RD11 AN19/T5CK/T8CK/RC4 5 56
dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T
dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/
dsPIC33FJXXXGPX06/X08/X10 Pin Diagrams (Continued) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 CSDO/RG13 CSDI/RG12 CSCK/RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant COFS/RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/
dsPIC33FJXXXGPX06/X08/X10 Table of Contents dsPIC33F Product Families ................................................................................................................................................................... 3 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers ..........
dsPIC33FJXXXGPX06/X08/X10 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest family reference sections of the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 FIGURE 1-1: dsPIC33FJXXXGPX06/X08/X10 GENERAL BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch DMA RAM 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 PORTB DMA 23 16 16 Controller 16 PORTC Address Generator Units Address Latch Program Memory EA MUX Data Latch PORTD ROM Latch 24 Instruction Decode
dsPIC33FJXXXGPX06/X08/X10 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN31 I Analog Pin Name Description Analog input channels. AVDD P P Positive supply for analog modules. This pin must be connected at all times. AVSS P P Ground reference for analog modules. CLKI CLKO I O CN0-CN23 I ST Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs.
dsPIC33FJXXXGPX06/X08/X10 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type RG0-RG3 RG6-RG9 RG12-RG15 I/O I/O I/O ST ST ST PORTG is a bidirectional I/O port. SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 I/O I O I/O I/O I O I/O ST ST — ST ST ST — ST Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out.
dsPIC33FJXXXGPX06/X08/X10 2.0 Note: 2.1 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”, which is available from the Microchip website (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic R1 MCLR C dsPIC33F VSS 10 Ω 2.2.1 VDD 0.1 µF Ceramic VSS VDD AVSS VDD AVDD 0.1 µF Ceramic VSS Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: • Device Reset • Device programming and debugging During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin.
dsPIC33FJXXXGPX06/X08/X10 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
dsPIC33FJXXXGPX06/X08/X10 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first.
dsPIC33FJXXXGPX06/X08/X10 3.0 Note: CPU This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 FIGURE 3-1: dsPIC33FJXXXGPX06/X08/X10 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 8 16 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 16 DMA RAM 16 DMA Controller Address Generator Units Address Latch 16 Program Memory EA MUX Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction R
dsPIC33FJXXXGPX06/X08/X10 FIGURE 3-2: dsPIC33FJXXXGPX06/X08/X10 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC33FJXXXGPX06/X08/X10 3.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disa
dsPIC33FJXXXGPX06/X08/X10 REGISTER 3-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit 0’ = Bit is cleared bit 11 bit 10-8 U-0 — R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATA bit 7 bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER R/W-1 SATDW R/W-0 ACCSAT C = Clear only bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read as ‘0’ US: DSP Multi
dsPIC33FJXXXGPX06/X08/X10 3.5 Arithmetic Logic Unit (ALU) 3.6 DSP Engine The dsPIC33FJXXXGPX06/X08/X10 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 Zero Backfill 16 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array DS70286C-page 28 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 3.6.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to 40 bits.
dsPIC33FJXXXGPX06/X08/X10 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and, thus, indicate that a catastrophic overflow has occurred.
dsPIC33FJXXXGPX06/X08/X10 3.6.2.4 Data Space Write Saturation 3.6.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder.
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 32 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 4.0 MEMORY ORGANIZATION Note: 4.1 This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 3. “Data Memory” (DS70202) and Section 4. “Program Memory” (DS70203) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJXXXGPX06/X08/X10 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 0x000000, with the actual address for the start of code at 0x000002.
dsPIC33FJXXXGPX06/X08/X10 4.2 Data Address Space The dsPIC33FJXXXGPX06/X08/X10 CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. Data memory maps of devices with different RAM sizes are shown in Figure 4-3 through Figure 4-5. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJXXXGPX06/X08/X10 DEVICES WITH 8 KBS RAM MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 8 Kbyte SRAM Space 0x17FF 0x1801 0x1FFF 0x2001 0x27FF 0x2801 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 DMA RAM 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70286C-page 36 0x27FE 0x2800 0xFFFE ©
dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJXXXGPX06/X08/X10 DEVICES WITH 16 KB RAM MSB Address LSB Address 16 bits MSB LSB 0x0000 0x0001 2 Kbyte SFR Space SFR Space 0x07FF 0x0801 0x1FFF X Data RAM (X) 0x27FF 0x2801 16 Kbyte SRAM Space 0x3FFF 0x4001 0x47FF 0x4801 0x07FE 0x0800 8 Kbyte Near Data Space 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE 0x4000 DMA RAM 0x8001 0x47FE 0x4800 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF © 2009 Mi
dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJXXXGPX06/X08/X10 DEVICES WITH 30 KB RAM MSB Address MSB 2 Kbyte SFR Space 0x0001 LSB Address 16 bits LSB 0x0000 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 30 Kbyte SRAM Space 0x47FF 0x4801 0x47FE 0x4800 Y Data RAM (Y) 0x77FF 0x7800 0x7FFF 0x8001 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF DS70286C-page 38 DMA RAM 0x77FE 0x7800 0x7FFE 0x8000 0xFFFE © 2009 Microch
dsPIC33FJXXXGPX06/X08/X10 4.2.5 X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
CPU CORE REGISTERS MAP SFR Name SFR Addr WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Register 11 00
© 2009 Microchip Technology Inc.
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXGPX10 DEVICES SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CNEN2 0062 — — — — — — — — CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CNPU1 0068 CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CNPU2 006A — — Legend: CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE —
© 2009 Microchip Technology Inc.
SFR Name SFR Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TMR2 0106 TON — TSIDL — — — TMR3HLD 0108 — — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF TGATE TCKPS<1:0> — TSYNC TCS — 0000 Timer2 Register xxxx Timer3 Holding Register (for 32-bit timer operations only) xxxx TMR3 010A Timer3 Register xxxx PR2 010C Period Register 2 FFFF
© 2009 Microchip Technology Inc.
SFR Name OUTPUT COMPARE REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 OC1RS 0180 Output Compare 1 Secondary Register OC1R 0182 Output Compare 1 Register OC1CON 0184 OC2RS 0186 Output Compare 2 Secondary Register OC2R 0188 Output Compare 2 Register OC2CON 018A OC3RS 018C Output Compare 3 Secondary Register OC3R 018E Output Compare 3 Register OC3CON 0190 OC4RS 0192 Output Compare 4 Secondary Register OC4R 0194 Output Compare 4
© 2009 Microchip Technology Inc.
SFR Name SFR Addr UART1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 2 Bit 1 All Resets STSEL 0000 URXDA 0110 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U1TXREG 0224 — — — — — — — UART Transmit Register xxxx U1RXREG 0226 — — — — — — — UART Receive Register 0000 U1BRG
© 2009 Microchip Technology Inc.
File Name Addr DMA REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 DMA0CON 0380 CHEN SIZE DIR HALF NULLW — — — — — DMA0REQ 0382 FORCE — — — — — — — — Bit 5 Bit 4 AMODE<1:0> Bit 3 Bit 2 — — Bit 1 Bit 0 MODE<1:0> IRQSEL<6:0> All Resets 0000 0000 DMA0STA 0384 STA<15:0> 0000 DMA0STB 0386 STB<15:0> 0000 DMA0PAD 0388 PAD<15:0> DMA0CNT 038A — — — — — — DMA1CON 038C CHEN SIZE DIR HALF NULLW — — — — DMA1REQ 038E
© 2009 Microchip Technology Inc.
File Name ECAN1 REGISTER MAP WHEN C1CTRL1.
© 2009 Microchip Technology Inc. TABLE 4-20: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.
File Name ECAN1 REGISTER MAP WHEN C1CTRL1.
© 2009 Microchip Technology Inc. TABLE 4-21: File Name ECAN2 REGISTER MAP WHEN C2CTRL1.
File Name Addr ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR dsPIC33FJXXXGP706/708/710 DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0500 051E Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x © 2009 Microchip Technology Inc.
© 2009 Microchip Technology Inc. TABLE 4-23: File Name Addr ECAN2 REGISTER MAP WHEN C2CTRL1.
DCI REGISTER MAP SFR Name Addr.
© 2009 Microchip Technology Inc.
PORTG REGISTER MAP(1) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISG 02E4 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF PORTG 02E6 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx LATG 02E8 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx
dsPIC33FJXXXGPX06/X08/X10 4.2.7 4.2.8 SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJXXXGPX06/X08/X10 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6.
dsPIC33FJXXXGPX06/X08/X10 TABLE 4-35: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Description The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the EA. Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
dsPIC33FJXXXGPX06/X08/X10 can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can only be configured to operate in one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer.
dsPIC33FJXXXGPX06/X08/X10 4.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than, the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes may, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-36: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0
dsPIC33FJXXXGPX06/X08/X10 4.6 Interfacing Program and Data Memory Spaces 4.6.1 Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The dsPIC33FJXXXGPX06/X08/X10 architecture uses a 24-bit wide program space and a 16-bit wide data space.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space Visibility(1) (Remapping) 0 EA 1 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces.
dsPIC33FJXXXGPX06/X08/X10 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
dsPIC33FJXXXGPX06/X08/X10 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 70 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 5.0 FLASH PROGRAM MEMORY Note: program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5.
dsPIC33FJXXXGPX06/X08/X10 5.2 RTSP Operation The dsPIC33FJXXXGPX06/X08/X10 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 25-12 illustrates typical erase and programming times.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 R/W-0(1) U-0 — ERASE U-0 — R/W-0(1) U-0 R/W-0(1) R/W-0(1) R/W-0(1) (2) — NVMOP<3:0> bit 7 bit 0 Legend: SO = Settable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit 1 = In
dsPIC33FJXXXGPX06/X08/X10 REGISTER 5-2: NVMKEY: NON-VOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: SO = Settable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (Write Only) bits DS70286C-page 74 x = Bit is
dsPIC33FJXXXGPX06/X08/X10 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data.
dsPIC33FJXXXGPX06/X08/X10 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_
dsPIC33FJXXXGPX06/X08/X10 6.0 Note: RESET This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
dsPIC33FJXXXGPX06/X08/X10 RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 TRAPR IOPUWR — — — — — VREGS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset
dsPIC33FJXXXGPX06/X08/X10 TABLE 6-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap conflict event POR, BOR IOPUWR (RCON<14>) Illegal opcode or uninitialized W register access POR, BOR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET instruction POR, BOR WDTO (RCON<4>) WDT time-out PWRSAV instruction, POR, BOR SLEEP (RCON<3>) PWRSAV #SLEEP instruction POR, BOR IDLE (RCON<2>) PWRSAV #IDLE instruction POR, BOR BOR (RCON<1>) BOR, POR — POR (RCO
dsPIC33FJXXXGPX06/X08/X10 TABLE 6-3: Reset Type RESET DELAY TIMES FOR VARIOUS DEVICE RESETS SYSRST Delay System Clock Delay FSCM Delay Notes TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TPOR + TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST TSTARTUP + TRST — TLOCK TOST TOST + TLOCK — TLOCK TOST TOST + TLOCK — TFSCM TFSCM TFSCM — TFSCM TFSCM TFSCM 1, 2, 3 1, 2, 3, 5, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 5, 6 3 3, 5, 6 3, 4, 6 3, 4, 5, 6 Clock Source POR EC, FRC, LPRC
dsPIC33FJXXXGPX06/X08/X10 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. “Interrupts” (DS70184) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS70286C-page 82 dsPIC33FJXXXGPX06/X08/X10 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interrupt Vector 117 Reserved Rese
dsPIC33FJXXXGPX06/X08/X10 TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IRQ) Number IVT Address AIVT Address 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002
dsPIC33FJXXXGPX06/X08/X10 TABLE 7-1: INTERRUPT VECTORS (CONTINUED) Vector Number Interrupt Request (IRQ) Number 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80-125 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72-117 TABLE 7-2: IVT Address AIVT Address Interrupt Source 0x000070 0x000170 0x000072 0x000172 0x000074 0x000174 0x000076 0x000176 0x000078 0x000178 0x00007A 0x00017A 0x00007C 0x00017C 0x00007E 0x00017E 0x000080 0x000180 0x000
dsPIC33FJXXXGPX06/X08/X10 7.3 Interrupt Control and Status Registers dsPIC33FJXXXGPX06/X08/X10 devices implement a total of 30 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC17 INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) IPL2(2) (2) IPL1 R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt P
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70286C
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector table
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA01IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplement
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microc
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA21IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IF IC7IF AD2IF INT1IF CNIF — MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UA
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T6IF DMA4IF — OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF DMA3IF C1IF C1RXIF SPI2IF SPI2EIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 T6IF: Timer6
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 2 C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Techno
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — — DMA5IF DCIIF DCIEIF — — C2IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2RXIF INT4IF INT3IF T9IF T8IF MI2C2IF SI2C2IF T7IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 C2TXIF C1TXIF DMA7IF DMA6IF — U2EIF U1EIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 C2TXIF: ECAN2 Transmit Data Re
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 IC8IE IC7IE AD2IE INT1IE CNIE — MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 U2TXIE: UART2 Transmitter I
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 Unimplemented: Read as ‘0’ bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microch
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T6IE DMA4IE — OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE DMA3IE C1IE C1RXIE SPI2IE SPI2EIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T6IE: Timer6 Interrupt Enable
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED) bit 2 C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — — DMA5IE DCIIE DCIEIE — — C2IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2RXIE INT4IE INT3IE T9IE T8IE MI2C2IE SI2C2IE T7IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 DMA5IE:
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 C2TXIE C1TXIE DMA7IE DMA6IE — U2EIE U1EIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 C2TXIE: ECAN2 Transmit Data Request Interrupt
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-15: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = I
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-16: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt P
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-17: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 — R/W-0 R/W-0 U1RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 DMA1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 AD1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Data
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-19: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 1
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-20: U-0 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 R/W-1 — R/W-0 R/W-0 IC8IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 IC7IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 AD2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC8IP<2:0>: Input Capture Channel 8 Interrupt Pr
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-21: U-0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-1 — R/W-0 R/W-0 T4IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 OC3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt P
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-22: U-0 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-1 — R/W-0 R/W-0 U2TXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 U2RXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T5IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priorit
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-23: U-0 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 R/W-1 — R/W-0 R/W-0 C1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 C1RXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI2IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 SPI2EIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 C1IP<2:0>: ECAN1 Event Interrupt Priority bits
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-24: U-0 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 R/W-1 — R/W-0 R/W-0 IC5IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 IC4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC3IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 DMA3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capture Cha
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-25: U-0 IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 R/W-1 — R/W-0 R/W-0 OC7IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC6IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 OC5IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 IC6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 OC7IP<2:0>: Output Compare Channel 7 Interrupt
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-26: U-0 IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 R/W-1 — R/W-0 R/W-0 T6IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 DMA4IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 OC8IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T6IP<2:0>: Timer6 Interrupt Priorit
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-27: U-0 IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 R/W-1 — R/W-0 R/W-0 T8IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 MI2C2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SI2C2IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T7IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T8IP<2:0>: Timer8 Interrupt Priority bits 111
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-28: U-0 IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 R/W-1 — R/W-0 R/W-0 C2RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 INT4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 INT3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 T9IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 C2RXIP<2:0>: ECAN2 Receive Data Ready Interru
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-29: U-0 IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 R/W-1 — R/W-0 R/W-0 DCIEIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 C2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 DCIEIP<2:0>: DCI Error Interrupt Priority bits 111 = Interrupt i
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-30: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 DMA5IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 DCIIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 DMA5IP<2:0>: DMA Channel 5 Data Transfer Co
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-31: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 U2EIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 U1EIP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 U2EIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interru
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-32: U-0 IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17 R/W-1 R/W-0 — R/W-0 C2TXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 C1TXIP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 DMA7IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 DMA6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 C2TXIP<2:0>: ECAN2 Tran
dsPIC33FJXXXGPX06/X08/X10 REGISTER 7-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is
dsPIC33FJXXXGPX06/X08/X10 7.4 Interrupt Setup Procedures 7.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 126 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 8.0 Note: DIRECT MEMORY ACCESS (DMA) This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 22. “Direct Memory Access (DMA)” (DS70182) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 FIGURE 8-1: TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS Peripheral Indirect Address DMA Control DMA Controller DMA RAM SRAM PORT 1 PORT 2 SRAM X-Bus DMA Ready Peripheral 3 DMA Channels CPU DMA DMA DS Bus CPU Peripheral DS Bus CPU Non-DMA Ready Peripheral CPU DMA DMA Ready Peripheral 1 CPU DMA DMA Ready Peripheral 2 Note: CPU and DMA address buses are not shown for clarity. 8.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CHEN SIZE DIR HALF NULLW — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 AMODE<1:0> U-0 U-0 — — R/W-0 R/W-0 MODE<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHEN: Channel Enable bit 1 = Channel enabled 0 = Channel disab
dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 FORCE(1) — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — IRQSEL6(2) IRQSEL5(2) R/W-0 R/W-0 IRQSEL4(2) IRQSEL3(2) R/W-0 R/W-0 R/W-0 IRQSEL2(2) IRQSEL1(2) IRQSEL0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FORCE: Force DMA T
dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-3: R/W-0 DMAxSTA: DMA CHANNEL x RAM START ADDRESS OFFSET REGISTER A R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown STA<15:0>: Primary DMA RAM Start Address bits (source or destination) REGISTER 8-4:
dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-5: R/W-0 DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PAD<15:0>: Peripheral Address Register bits Note 1: If the channel is enabled (i.e.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-7: DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED) bit 3 XWCOL3: Channel 3 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 2 XWCOL2: Channel 2 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected 0 = No write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit
dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-8: DMACS1: DMA CONTROLLER STATUS REGISTER 1 U-0 U-0 U-0 U-0 — — — — R-1 R-1 R-1 R-1 LSTCH<3:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 LSTCH<3:0>: Last DMA Channel Active bits 1111 = No D
dsPIC33FJXXXGPX06/X08/X10 REGISTER 8-9: R-0 DSADR: MOST RECENT DMA RAM ADDRESS R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits DS70286C-page 136 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 9.0 OSCILLATOR CONFIGURATION Note: This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Oscillator” (DS70186) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 9.1 CPU Clocking System There are seven system clock options provided by the dsPIC33FJXXXGPX06/X08/X10: • • • • • • • FRC Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Secondary (LP) Oscillator LPRC Oscillator FRC Oscillator with postscaler 9.1.1 SYSTEM CLOCK SOURCES The FRC (Fast RC) internal oscillator runs at a nominal frequency of 7.37 MHz. The user software can tune the FRC frequency.
dsPIC33FJXXXGPX06/X08/X10 EQUATION 9-3: For example, suppose a 10 MHz crystal is being used, with “XT with PLL” being the selected oscillator mode. If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO input of 10/2 = 5 MHz, which is within the acceptable range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then M = 32. This yields a VCO output of 5 x 32 = 160 MHz, which is within the 100-200 MHz range needed.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 9-1: U-0 OSCCON: OSCILLATOR CONTROL REGISTER(1) R-0 — R-0 R-0 COSC<2:0> U-0 R/W-y R/W-y R/W-y NOSC<2:0>(2) — bit 15 bit 8 R/W-0 U-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0 CLKLOCK — LOCK — CF — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read a
dsPIC33FJXXXGPX06/X08/X10 REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Writes to this register require an unlock sequence. Refer to Section 7.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 9-2: R/W-0 CLKDIV: CLOCK DIVISOR REGISTER R/W-0 ROI R/W-1 R/W-1 R/W-0 R/W-0 (1) DOZE<2:0> DOZEN R/W-0 R/W-0 FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 PLLPOST<1:0> U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on I
dsPIC33FJXXXGPX06/X08/X10 REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0(1) — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted
dsPIC33FJXXXGPX06/X08/X10 REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 = Center frequency + 11.625% (8.
dsPIC33FJXXXGPX06/X08/X10 9.2 Clock Switching Operation Applications are free to switch between any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects that could result from this flexibility, dsPIC33FJXXXGPX06/X08/X10 devices have a safeguard lock built into the switch process. Note: 9.2.1 Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMD<1:0> Configuration bits.
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 146 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 10.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 10.2.2 IDLE MODE Idle mode has these features: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.4 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 T5MD T4MD T3MD T2MD T1MD — — DCIMD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD AD1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T5MD: Timer5 Module Disable bit 1 =
dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 1 C1MD: ECAN2 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled DS70286C-page 150 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 IC8MD: Input Captu
dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 (CONTINUED) bit 3 OC4MD: Output Compare 4 Module Disable bit 1 = Output Compare 4 module is disabled 0 = Output Compare 4 module is enabled bit 2 OC3MD: Output Compare 3 Module Disable bit 1 = Output Compare 3 module is disabled 0 = Output Compare 3 module is enabled bit 1 OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Ou
dsPIC33FJXXXGPX06/X08/X10 REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 T9MD T8MD T7MD T6MD — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — I2C2MD AD2MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T9MD: Timer9 Module Disable bit 1 = Timer9 module is disabled 0 = Timer9 module i
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 154 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 11.0 Note: I/O PORTS This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “I/O Ports” (DS70193) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 11.2 Open-Drain Configuration In addition to the PORT, LAT and TRIS registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g.
dsPIC33FJXXXGPX06/X08/X10 12.0 Note: TIMER1 Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 R/W-0 R/W-0 U-0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read a
dsPIC33FJXXXGPX06/X08/X10 13.0 Note: TIMER2/3, TIMER4/5, TIMER6/7 AND TIMER8/9 This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 TIMER2/3 (32-BIT) BLOCK DIAGRAM(1) FIGURE 13-1: T2CK 1x Gate Sync 01 TCY 00 TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 TGATE TCS TGATE Q 1 Set T3IF Q D CK 0 PR3 ADC Event Trigger(2) Equal PR2 Comparator MSb LSb TMR3 Reset TMR2 Sync 16 Read TMR2 Write TMR2 16 TMR3HLD 16 16 Data Bus<15:0> Note 1: 2: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 13-2: TIMER2 (16-BIT) BLOCK DIAGRAM TON T2CK TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS TCY 1 Set T2IF 0 Reset Equal Q D Q CK TMR2 TGATE Sync Comparator PR2 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 13-1: TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> R/W-0 T32 U-0 — R/W-0 (1) TCS bit 7 U-0 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When T32 = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit
dsPIC33FJXXXGPX06/X08/X10 REGISTER 13-2: TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(2) — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE(1) R/W-0 R/W-0 TCKPS<1:0>(1) U-0 U-0 R/W-0 U-0 — — TCS(1,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 164 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 14.0 INPUT CAPTURE Note: 2. This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 14.
dsPIC33FJXXXGPX06/X08/X10 15.0 OUTPUT COMPARE Note: The state of the output pin changes when the timer value matches the Compare register value. The output compare module generates either a single output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events. The output compare module can also generate interrupts on compare match events. This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 families of devices.
dsPIC33FJXXXGPX06/X08/X10 15.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 15-1 lists the different bit settings for the Output Compare modes. Figure 15-2 illustrates the output compare operation for various modes.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 — — — OCFLT OCTSEL R/W-0 R/W-0 R/W-0 OCM<2:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Stop O
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 170 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note: This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18. “Serial Peripheral Interface (SPI)” (DS70206) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enables module and confi
dsPIC33FJXXXGPX06/X08/X10 REGISTER 16-2: U-0 — bit 15 R/W-0 SSEN(3) bit 7 SPIXCON1: SPIx CONTROL REGISTER 1 U-0 — U-0 — R/W-0 DISSCK R/W-0 CKP R/W-0 MSTEN R/W-0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 W = Writable bit ‘1’ = Bit is set R/W-0 DISSDO R/W-0 SPRE<2:0>(2) R/W-0 MODE16 R/W-0 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 R/W-0 PPRE<1:0>(2) bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Uni
dsPIC33FJXXXGPX06/X08/X10 REGISTER 16-2: bit 4-2 bit 1-0 SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as fram
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 176 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 17.0 Note: INTER-INTEGRATED CIRCUIT™ (I2C™) This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS70286C-page 178 © 2009 M
dsPIC33FJXXXGPX06/X08/X10 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Set in hardware HC = Cleared in hardware -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit i
dsPIC33FJXXXGPX06/X08/X10 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0 HSC R-0 HSC U-0 U-0 U-0 R/C-0 HS R-0 HSC R-0 HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC R-0 HSC R-0 HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ C = Clear only bit R = Readable bit W = Writable bit HS = Set in hardware HSC = Hardware set/cleared -n = Value at POR ‘1’ = Bit is s
dsPIC33FJXXXGPX06/X08/X10 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 184 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 18.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “UART” (DS70188) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 UARTEN(1) — USIDL IREN(2) RTSMD — R/W-0 R/W-0 UEN<1:0> bit 15 bit 8 R/W-0 HC R/W-0 R/W-0 HC R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH R/W-0 R/W-0 PDSEL<1:0> R/W-0 STSEL bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UART
dsPIC33FJXXXGPX06/X08/X10 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00
dsPIC33FJXXXGPX06/X08/X10 REGISTER 18-2: R/W-0 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 UTXISEL1 UTXINV R/W-0 UTXISEL0 U-0 — R/W-0 HC R/W-0 R-0 R-1 UTXBRK UTXEN(1) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0> R/W-0 R-1 R-0 R-0 R/C-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit
dsPIC33FJXXXGPX06/X08/X10 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled.
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 190 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 19.0 Note: 19.1 ENHANCED CAN (ECAN™) MODULE This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Enhanced Controller Area Network (ECAN™)” (DS70185) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 FIGURE 19-1: ECAN™ MODULE BLOCK DIAGRAM RXF15 Filter RXF14 Filter RXF13 Filter RXF12 Filter DMA Controller RXF11 Filter RXF10 Filter RXF9 Filter RXF8 Filter TRB7 TX/RX Buffer Control Register RXF7 Filter TRB6 TX/RX Buffer Control Register RXF6 Filter TRB5 TX/RX Buffer Control Register RXF5 Filter TRB4 TX/RX Buffer Control Register RXF4 Filter TRB3 TX/RX Buffer Control Register RXF3 Filter TRB2 TX/RX Buffer Control Register RXF2 Filter RXM2 Mask TRB1 TX/RX Buffer Con
dsPIC33FJXXXGPX06/X08/X10 19.3 Modes of Operation Note: The CAN module can operate in one of several operation modes selected by the user. These modes include: • • • • • • Initialization Mode Disable Mode Normal Operation Mode Listen Only Mode Listen All Messages Mode Loopback Mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL1<10:8>). Entry into a mode is Acknowledged by monitoring the OPMODE<2:0> bits (CiCTRL1<7:5>).
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-1: CiCTRL1: ECAN™ CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 r-0 — — CSIDL ABAT — R/W-1 R/W-0 R/W-0 REQOP<2:0> bit 15 bit 8 R-1 R-0 R-0 OPMODE<2:0> U-0 R/W-0 U-0 U-0 R/W-0 — CANCAP — — WIN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared r = Bit is Reserved bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: Stop in Idle Mode bit 1 = Dis
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-2: CiCTRL2: ECAN™ CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 DNCNT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare u
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 FILHIT<4:0> bit 15 bit 8 U-0 R-1 R-0 R-0 — R-0 R-0 R-0 R-0 ICODE<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit Number bits 10000-11111 = Reserved 01111 = Filter 15 x = Bit is unknown
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-4: R/W-0 CiFCTRL: ECAN™ FIFO CONTROL REGISTER R/W-0 R/W-0 DMABS<2:0> U-0 U-0 U-0 U-0 U-0 — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in DMA RAM 101 = 24 buffers in DMA RAM 100 = 16
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-5: CiFIFO: ECAN™ FIFO STATUS REGISTER U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 FBP<5:0> bit 15 bit 8 U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 FNRB<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Write Buffer Pointer bits 011111 = RB31 buffer 011110 = RB30 buffer x = Bit is unknown
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-6: CiINTF: ECAN™ INTERRUPT FLAG REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWAR RXWAR EWARN bit 15 bit 8 R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXBO
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7 IVRIE: Invalid Message Received Interrupt Enab
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-8: R-0 CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RERRCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 TERRCNT<7:0>: Transmit Error Count bits bit 7-0 RERRCNT<7:0>: Receive Error Count bits © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-9: CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW<1:0> R/W-0 R/W-0 R/W-0 BRP<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-6 SJW<1:0>: Synchronization Jump Width bits 11 = Length is 4 x TQ 1
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-10: CiCFG2: ECAN™ BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 — WAKFIL — — — R/W-x R/W-x R/W-x SEG2PH<2:0> bit 15 bit 8 R/W-x R/W-x SEG2PHTS SAM R/W-x R/W-x R/W-x SEG1PH<2:0> R/W-x R/W-x R/W-x PRSEG<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 WAKFIL: Sele
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-11: CiFEN1: ECAN™ ACCEPTANCE FILTER ENABLE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8 bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN7 FLTEN6 FLTEN5 FLTEN4 FLTEN3 FLTEN2 FLTEN1 FLTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-13: CiBUFPNT2: ECAN™ FILTER 4-7 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP<3:0> R/W-0 R/W-0 R/W-0 F6BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP<3:0> R/W-0 R/W-0 R/W-0 F4BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits bit 11-8 F6BP<3:0>: RX Buffe
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-15: CiBUFPNT4: ECAN™ FILTER 12-15 BUFFER POINTER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP<3:0> R/W-0 R/W-0 R/W-0 F14BP<3:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP<3:0> R/W-0 R/W-0 R/W-0 F12BP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits bit 11-8 F14BP<3:0>:
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-16: CiRXFnSID: ECAN™ ACCEPTANCE FILTER n STANDARD IDENTIFIER (n = 0, 1, ...
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER R/W-0 R/W-0 F7MSK<1:0> R/W-0 R/W-0 R/W-0 F6MSK<1:0> R/W-0 R/W-0 F5MSK<1:0> R/W-0 F4MSK<1:0> bit 15 bit 8 R/W-0 R/W-0 F3MSK<1:0> R/W-0 R/W-0 R/W-0 F2MSK<1:0> R/W-0 R/W-0 F1MSK<1:0> R/W-0 F0MSK<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 F7MSK<1:0>: Mask Source for Fi
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER R/W-0 R/W-0 F15MSK<1:0> bit 15 R/W-0 R/W-0 F14MSK<1:0> R/W-0 R/W-0 F13MSK<1:0> R/W-0 R/W-0 F12MSK<1:0> bit 8 R/W-0 R/W-0 F11MSK<1:0> bit 7 R/W-0 R/W-0 F10MSK<1:0> R/W-0 R/W-0 F9MSK<1:0> R/W-0 R/W-0 F8MSK<1:0> bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 bit 1-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bi
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 SID<10:0>
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-22: CiRXFUL1: ECAN™ RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-24: CiRXOVF1: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ =
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-26: CiTRmnCON: ECAN™ TX/RX BUFFER m CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn R/W-0 R/W-0 TXnPRI<1:0> bit 15 bit 8 R/W-0 R-0 TXENm TXABTm(1) R-0 R-0 (1) TXLARBm TXERRm (1) R/W-0 R/W-0 TXREQm RTRENm R/W-0 R/W-0 TXmPRI<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is
dsPIC33FJXXXGPX06/X08/X10 Note: The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM. REGISTER 19-27: CiTRBnSID: ECAN™ BUFFER n STANDARD IDENTIFIER (n = 0, 1, ...
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-29: CiTRBnDLC: ECAN™ BUFFER n DATA LENGTH CONTROL (n = 0, 1, ...
dsPIC33FJXXXGPX06/X08/X10 REGISTER 19-31: CiTRBnSTAT: ECAN™ RECEIVE BUFFER n STATUS (n = 0, 1, ...
dsPIC33FJXXXGPX06/X08/X10 20.0 Note: 20.1 DATA CONVERTER INTERFACE (DCI) MODULE This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20. “Data Converter Interface (DCI)” (DS70288) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJXXXGPX06/X08/X10 FIGURE 20-1: DCI MODULE BLOCK DIAGRAM BCG Control bits SCKD FOSC/4 Sample Rate CSCK Generator FSD Word Size Selection bits Frame Length Selection bits 16-bit Data Bus DCI Mode Selection bits Frame Synchronization Generator COFS Receive Buffer Registers w/Shadow DCI Buffer Control Unit 15 Transmit Buffer Registers w/Shadow 0 DCI Shift Register CSDI CSDO DS70286C-page 218 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 20-1: DCICON1: DCI CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 DCIEN — DCISIDL — DLOOP CSCKD CSCKE COFSD bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 UNFM CSDOM DJST — — — R/W-0 R/W-0 COFSM<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DCIEN: DCI Module Enable bit 1 = Module is enable
dsPIC33FJXXXGPX06/X08/X10 REGISTER 20-2: DCICON2: DCI CONTROL REGISTER 2 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 U-0 R/W-0 — COFSG3 BLEN<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 COFSG<2:0> U-0 R/W-0 — R/W-0 R/W-0 R/W-0 WS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-10 BLEN<1:0>: Buffer Length Control bits 11 = Four data words wi
dsPIC33FJXXXGPX06/X08/X10 REGISTER 20-3: DCICON3: DCI CONTROL REGISTER 3 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 BCG<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BCG<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 BCG<11:0>: DCI Bit Clock Generator Control bits © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 20-4: DCISTAT: DCI STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 SLOT<3:0> bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ROV RFUL TUNF TMPTY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 SLOT<3:0>: DCI Slot Status bits 1111 = Slot #15 is currently act
dsPIC33FJXXXGPX06/X08/X10 REGISTER 20-5: RSCON: DCI RECEIVE SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown RSE<15:0>: Recei
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 224 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 21.0 Note: 10-BIT/12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). analog input pins.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 21-1: ADCx MODULE BLOCK DIAGRAM AN0 ANy(3) S/H0 CHANNEL SCAN + CH0SA<4:0> CH0 CH0SB<4:0> - CSCNA AN1 VREF- CH0NA CH0NB VREF+(1) AVDD VREF-(1) AVSS AN0 AN3 S/H1 + - CH123SA CH123SB CH1(2) AN6 AN9 VREF- VREFH VREFL CH123NA CH123NB SAR ADC ADC1BUF0 AN1 AN4 S/H2 + CH123SA CH123SB CH2(2) - AN7 AN10 VREF- CH123NA CH123NB AN2 AN5 S/H3 + CH123SA CH123SB CH3(2) - AN8 AN11 VREF- CH123NA CH123NB Alternate Input Selection Note 1: 2: 3: VREF+, VREF- inputs
dsPIC33FJXXXGPX06/X08/X10 FIGURE 21-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADxCON3<15> ADC Internal RC Clock(2) 0 TAD ADxCON3<5:0> 1 6 TOSC(1) X2 TCY ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 64 Note 1: 2: Refer to Figure 9-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock source frequency. TOSC = 1/FOSC. See the ADC electrical specifications for the exact RC clock value. © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B R/W-0 R/W-0 FORM<1:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 SSRC<2:0> U-0 R/W-0 R/W-0 R/W-0 HC,HS R/C-0 HC, HS — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Cleared by hardware HS = Set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cle
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2) (CONTINUED) bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x) When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’ 1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01) 0 = Samples multiple channels individually in sequence bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-2: R/W-0 ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2) R/W-0 R/W-0 VCFG<2:0> U-0 U-0 R/W-0 — — CSCNA R/W-0 R/W-0 CHPS<1:0> bit 15 bit 8 R-0 U-0 BUFS — R/W-0 R/W-0 R/W-0 R/W-0 SMPI<3:0> R/W-0 R/W-0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Converter Voltage Reference Configurat
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-3: ADxCON3: ADCx CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMC<4:0>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from system clock bit 14-13 U
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-4: ADxCON4: ADCx CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 DMABL<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog In
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NB<1:0> R/W-0 CH123SB bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 CH123NA<1:0> R/W-0 CH123SA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SB<4:0> bit 15 bit 8 R/W-0 U-0 U-0 CH0NA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0SA<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit Same definition as bit 7.
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unkno
dsPIC33FJXXXGPX06/X08/X10 REGISTER 21-9: AD1PCFGH: ADC1 PORT CONFIGURATION REGISTER HIGH(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15
dsPIC33FJXXXGPX06/X08/X10 22.0 SPECIAL FEATURES Note: 22.1 The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000. This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23.
dsPIC33FJXXXGPX06/X08/X10 TABLE 22-2: dsPIC33FJXXXGPX06/X08/X10 CONFIGURATION BITS DESCRIPTION Bit Field Register Description BWRP FBS Boot Segment Program Flash Write Protection 1 = Boot segment may be written 0 = Boot segment is write-protected BSS<2:0> FBS Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 1K IW less VS 110 = Standard security; boot program Flash segment starts at End of VS, ends at 0007FEh 010 = High security; boot program Flash s
dsPIC33FJXXXGPX06/X08/X10 TABLE 22-2: dsPIC33FJXXXGPX06/X08/X10 CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register SSS<2:0> FSS Description Secure Segment Program Flash Code Protection Size (FOR 128K and 256K DEVICES) X11 = No Secure program Flash segment Secure space is 8K IW less BS 110 = Standard security; secure program Flash segment starts at End of BS, ends at 0x003FFE 010 = High security; secure program Flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less B
dsPIC33FJXXXGPX06/X08/X10 TABLE 22-2: dsPIC33FJXXXGPX06/X08/X10 CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register IESO FOSCSEL Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC<2:0> FOSCSEL Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator with postscaler 110 = Internal Fast RC (FRC) oscillator with
dsPIC33FJXXXGPX06/X08/X10 22.2 On-Chip Voltage Regulator All of the dsPIC33FJXXXGPX06/X08/X10 devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the dsPIC33FJXXXGPX06/X08/X10 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins.
dsPIC33FJXXXGPX06/X08/X10 22.4 Watchdog Timer (WDT) For dsPIC33FJXXXGPX06/X08/X10 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler and then can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit.
dsPIC33FJXXXGPX06/X08/X10 22.5 JTAG Interface 22.8 In-Circuit Debugger dsPIC33FJXXXGPX06/X08/X10 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on the interface will be provided in future revisions of the document. When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE.
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 244 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 23.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJXXXGPX06/X08/X10 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the “dsPIC33F Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The dsPIC33F instruction set is identical to that of the dsPIC30F.
dsPIC33FJXXXGPX06/X08/X10 All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP.
dsPIC33FJXXXGPX06/X08/X10 TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0..W15} Wnd One of 16 destination working registers ∈ {W0...W15} Wns One of 16 source working registers ∈ {W0...
dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: Base Instr # 1 2 3 4 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR Assembly Syntax Description # of # of Words Cycles Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z OA,OB,SA,SB ADD W
dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: Base Instr # 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,#bit4 Bit Test f 1 1 Z
dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
dsPIC33FJXXXGPX06/X08/X10 TABLE 23-2: Base Instr # 66 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC SAC Assembly Syntax Description # of # of Words Cycles Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC33FJXXXGPX06/X08/X10 24.
dsPIC33FJXXXGPX06/X08/X10 24.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
dsPIC33FJXXXGPX06/X08/X10 24.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
dsPIC33FJXXXGPX06/X08/X10 24.11 PICSTART Plus Development Programmer 24.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
dsPIC33FJXXXGPX06/X08/X10 25.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJXXXGPX06/X08/X10 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJXXXGPX06/X08/X10 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
dsPIC33FJXXXGPX06/X08/X10 25.1 DC Characteristics TABLE 25-1: OPERATING MIPS VS. VOLTAGE Characteristic DC5 TABLE 25-2: Max MIPS VDD Range (in Volts) Temp Range (in °C) dsPIC33FJXXXGPX06/X08/X10 3.0-3.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Operating Voltage DC10 Supply Voltage VDD — 3.0 — 3.6 V — DC12 VDR RAM Data Retention Voltage(2) 1.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage DI10 I/O pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 I/O Pins with OSC1 or SOSCI VSS — 0.2 VDD V DI18 2 I/O Pins with I C VSS — 0.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param Symbol No. VOL DO10 DO16 VOH Characteristic Min Typ Max Units Conditions I/O ports — — 0.4 V IOL = 2 mA, VDD = 3.3V OSC2/CLKO — — 0.4 V IOL = 2 mA, VDD = 3.3V Output Low Voltage Output High Voltage DO20 I/O ports 2.40 — — V IOH = -2.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Program Flash Memory D130a EP Cell Endurance 100 1000 — D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.
dsPIC33FJXXXGPX06/X08/X10 25.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33FJXXXGPX06/X08/X10 AC characteristics and timing parameters. TABLE 25-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Operating voltage VDD range as described in Section 25.0 “Electrical Characteristics”.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS25 OS30 OS31 OS31 CLKO OS41 OS40 TABLE 25-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units Conditions OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range(2) 0.8 — 8.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 25-1 for load conditions. TABLE 25-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out OSC Time-out SY11 SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 25-1 for load conditions. DS70286C-page 270 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Param Symbol No.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-5: TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 25-1 for load conditions. TABLE 25-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-23: TIMER2, TIMER4, TIMER6 AND TIMER8 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. TB10 TB11 TB15 TB20 Symbol TtxH TtxL TtxP TCKEXTMRL Characteristic TxCK High Time TxCK Low Time TxCK Input Period Min Typ Max Units Conditions Synchronous, no prescaler 0.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 25-1 for load conditions. TABLE 25-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No. Symbol IC10 TccL Characteristic(1) ICx Input Low Time No Prescaler Min Max Units Conditions 0.5 TCY + 20 — ns — 10 — ns 0.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 25-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-9: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP31 SDIx MSb In LSb SP30 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 25-1 for load conditions. TABLE 25-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-10: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 SP40 SDIX LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 25-1 for load conditions. TABLE 25-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions. TABLE 25-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-12: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDI SDIx MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions. © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-13: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 25-1 for load conditions. FIGURE 25-14: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 25-1 for load conditions. © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param Symbol No.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-15: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 25-16: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 IS40 IS45 IS50 Note Symbol Characteristic TLO:SCL Clock Low Time THI:SCL Clock High Time Min Max Units 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs 1 MHz mode(1) 100 kHz mode 0.5 4.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-17: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CS20 CS21 CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CSDO 70 CS50 High-Z LSb MSb CS30 CSDI MSb In High-Z CS31 LSb In CS40 CS41 Note: Refer to Figure 25-1 for load conditions. © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-34: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-18: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS75 CS76 CS80 SDOx (CSDO) MSb LSb LSb CS76 CS75 MSb In SDIx (CSDI) CS65 CS66 TABLE 25-35: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-19: CiTx Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 25-36: ECAN™ MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C AC CHARACTERISTICS Param No.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-37: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD - 0.3 or 3.0 — Lesser of VDD + 0.3 or 3.6 V — AD02 AVSS Module VSS Supply VSS - 0.3 — VSS + 0.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-38: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions ADC Accuracy (12-bit Mode) - Measurements with external VREF+/VREFAD20a Nr Resolution 12 data bits bits AD21a INL Integral Nonlinearity -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-39: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions ADC Accuracy (10-bit Mode) - Measurements with external VREF+/VREFAD20b Nr Resolution 10 data bits bits AD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-20: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 TSAMP AD55 CONV ADxIF Buffer(0) 1 2 3 4 5 6 1 – Software sets ADxCON. SAMP to start sampling. 7 8 9 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described in Section 16.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-40: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. Symbol AD50a TAD AD51a tRC AD55a tCONV AD56a FCNV AD57a TSAMP AD60a tPCS Characteristic Min. Typ(1) Max. Clock Parameters ADC Clock Period 117.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-21: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 16.
dsPIC33FJXXXGPX06/X08/X10 FIGURE 25-22: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc TSAMP AD55 TSAMP AD55 TCONV CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period.
dsPIC33FJXXXGPX06/X08/X10 TABLE 25-41: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max. Units Conditions Clock Parameters AD50b TAD ADC Clock Period 65 — — ns — AD51b TRC ADC Internal RC Oscillator Period — 250 — ns — AD55b TCONV Conversion Time Conversion Rate — 12 TAD — — — — — 1.
dsPIC33FJXXXGPX06/X08/X10 26.0 PACKAGING INFORMATION 26.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC33FJ 256GP706 -I/PT e3 0510017 80-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN e3 * Note: Example dsPIC33FJ256 GP710-I/PT e3 0510017 100-Lead TQFP (14x14x1mm) Legend: XX...
dsPIC33FJXXXGPX06/X08/X10 26.2 Package Details 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 64 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.
dsPIC33FJXXXGPX06/X08/X10 ' ( !" #$ % & ! " #! $ ! % & ' #( # # ! ) % * ! ! & ! !! +,,''' " ", % © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 80 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.
dsPIC33FJXXXGPX06/X08/X10 ) ' ( # # !" #$ % & ! " #! $ ! % & ' #( # # ! ) % * ! ! & ! !! +,,''' " ", % © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 100-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 Units Dimension Limits Number of Leads A2 L1 MILLIMETERS MIN N NOM MAX 100 Lead Pitch e Overall Height A – 0.40 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.
dsPIC33FJXXXGPX06/X08/X10 ' ( # # !" #$ % & ! " #! $ ! % & ' #( # # ! ) % * ! ! & ! !! +,,''' " ", % © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 100-Lead Plastic Thin Quad Flatpack (PF) – 14x14x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 100 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.
dsPIC33FJXXXGPX06/X08/X10 ' ( !" #$ % & ! " #! $ ! % & ' #( # # ! ) % * ! ! & ! !! +,,''' " ", % © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 306 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 APPENDIX A: REVISION HISTORY Revision A (October 2006) Initial release of this document. Revision B (March 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description Section 1.0 “Device Overview” Added External Interrupt pin information (INT0 through INT4) to Table 1-1. Section 3.
dsPIC33FJXXXGPX06/X08/X10 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 8.0 “Oscillator Configuration” Update Description Updated the third clock source item (External Clock) in Section 8.1.1 “System Clock sources”. Added the center frequency in the OSCTUN register for the FRC Tuning bits (TUN<5:0>) value 011111 and updated the center frequency for bits value 011110 (Register 8-4). Section 15.
dsPIC33FJXXXGPX06/X08/X10 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 24.0 “Electrical Characteristics” Update Description Updated typical value for parameter AD08 (Table 24-37). Updated minimum and maximum (both internal and external VREF+/VREF-) values for parameter AD21a (Table 24-38). Updated minimum, typical, and maximum (external VREF+/VREF-) values for parameter AD24a (Table 24-38). Updated maximum value for parameter AD32a (Table 24-38).
dsPIC33FJXXXGPX06/X08/X10 Revision C (March 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE The other changes are referenced by their respective section in the following table.
dsPIC33FJXXXGPX06/X08/X10 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 19.0 “Enhanced CAN (ECAN™) Module” Update Description Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (see Register 19-1). Added the ECAN Filter 15-8 Mask Selection (CiFMSKSEL2) register (see Register 19-19). Section 21.0 “10-Bit/12-Bit Analog-to-Digital Converter (ADC)” Replaced the ADC Module Block Diagram (see Figure 21-1) and removed Figure 21-2. Section 22.
dsPIC33FJXXXGPX06/X08/X10 NOTES: DS70286C-page 312 © 2009 Microchip Technology Inc.
dsPIC33FJXXXGPX06/X08/X10 INDEX A A/D Converter ................................................................... 225 DMA .......................................................................... 225 Initialization ............................................................... 225 Key Features............................................................. 225 AC Characteristics ............................................................ 266 Internal RC Accuracy ...........................................
dsPIC33FJXXXGPX06/X08/X10 ECAN2 Register Map (C2CTRL1.WIN = 0 or 1) ......... 55 ECAN2 Register Map (C2CTRL1.WIN = 0) .......... 55, 56 Frame Types ............................................................. 191 Modes of Operation .................................................. 193 Overview ................................................................... 191 ECAN Registers Filter 15-8 Mask Selection Register (CiFMSKSEL2). 209 Electrical Characteristics................................................
dsPIC33FJXXXGPX06/X08/X10 Clock Frequency and Switching................................ 147 Program Address Space ..................................................... 33 Construction................................................................ 66 Data Access from Program Memory Using Program Space Visibility.................................................... 69 Data Access from Program Memory Using Table Instructions ....................................................................
dsPIC33FJXXXGPX06/X08/X10 SPIxSTAT (SPIx Status and Control) ....................... 172 SR (CPU Status) ................................................... 24, 86 T1CON (Timer1 Control)........................................... 158 TSCON (DCI Transmit Slot Control) ......................... 223 TxCON (T2CON, T4CON, T6CON or T8CON Control) .. 162 TyCON (T3CON, T5CON, T7CON or T9CON Control) .. 163 UxMODE (UARTx Mode) .......................................... 186 UxSTA (UARTx Status and Control) ..........
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dsPIC33FJXXXGPX06/X08/X10 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 256 GP7 10 T I / PT - XXX Examples: a) Microchip Trademark Architecture dsPIC33FJ256GP710I/PT: General-purpose dsPIC33, 64 KB program memory, 100-pin, Industrial temp., TQFP package.
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