Datasheet

 2011-2012 Microchip Technology Inc. DS70652E-page 31
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
AVDD P P No Positive supply for analog modules. This pin must be connected at all times.
AVDD is connected to VDD in the 18-pin dsPIC33FJXXGP101 and 20-pin
dsPIC33FJXXMC101 devices. In all other devices, AVDD is separated from
V
DD.
AV
SS P P No Ground reference for analog modules. AVSS is connected to VSS in the
18-pin dsPIC33FJXXGP101 and 20-pin dsPIC33FJXXMC101 devices. In all
other devices, AV
SS is separated from VSS.
V
DD P — No Positive supply for peripheral logic and I/O pins.
VCAP P — No CPU logic filter capacitor connection.
V
SS P — No Ground reference for logic and I/O pins.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1
pin on dsPIC33FJXXMC101 (20-pin) devices.
2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only.
3: The FLTB1
pin is available in dsPIC(16/32)MC102/104 devices only.
4: The PWM Fault pins are enabled during any Reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM Faults.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
6: This pin is available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.