Datasheet
2011-2012 Microchip Technology Inc. DS70652E-page 259
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
23.0 SPECIAL FEATURES
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices include several features
intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
23.1 Configuration Bits
The Configuration Shadow register bits can be config-
ured (read as ‘0’) or left unprogrammed (read as ‘1’) to
select various device configurations. These read-only
bits are mapped starting at program memory location,
0xF80000. A detailed explanation of the various bit
functions is provided in Table 23-4.
Note that address 0xF80000 is beyond the user pro-
gram memory space and belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads.
In dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices, the
configuration bytes are implemented as volatile memory.
This means that configuration data must be
programmed each time the device is powered up. Con-
figuration data is stored in the two words at the top of the
on-chip program memory space, known as the Flash
Configuration Words. Their specific locations are shown
in Table 23-2. These are packed representations of the
actual device Configuration bits, whose actual locations
are distributed among several locations in configuration
space. The configuration data is automatically loaded
from the Flash Configuration Words to the proper
Configuration registers during device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper byte of all Flash Configuration Words in pro-
gram memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
Note 1: This data sheet summarizes the
features of the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 24. “Pro-
gramming and Diagnostics” (DS70207)
and Section 25. “Device Configuration”
(DS70194) in the “dsPIC33F/PIC24H
Family Reference Manual”, which are
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Configuration data is reloaded on all types
of device Resets.
Note: Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.