Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 98  2011-2012 Microchip Technology Inc.
TABLE 7-2: TRAP VECTORS
7.3 Interrupt Control and Status
Registers
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices implement
a total of 22 registers for the interrupt controller:
• INTCON1
• INTCON2
•IFSx
•IECx
•IPCx
•INTTREG
7.3.1 INTCON1 AND INTCON2
Global interrupt functions are controlled from INTCON1
and INTCON2. INTCON1 contains the Interrupt Nest-
ing Disable (NSTDIS) bit as well as the control and
status flags for the processor trap sources. The
INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.2 IFSx Registers
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
7.3.3 IECx Registers
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.3.4 IPCx Registers
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
7.3.5 INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into Vector Number
(VECNUM<6:0>) and Interrupt Level (ILR<3:0>) bit
fields in the INTTREG register. The new Interrupt
Priority Level is the priority of the pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Tab l e 7- 1 . For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IPx
bits in the first positions of IPC0 (IPC0<2:0>).
7.3.6 STATUS/CONTROL REGISTERS
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
• The CPU STATUS Register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user
application can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU Interrupt Priority Level. IPL3 is a
read-only bit so that trap events cannot be
masked by the user software.
All Interrupt registers are described in Register 7-1
through Register 7-28 in the following pages.
Vector Number IVT Address AIVT Address Trap Source
0 0x000004 0x000104 Reserved
1 0x000006 0x000106 Oscillator Failure
2 0x000008 0x000108 Address Error
3 0x00000A 0x00010A Stack Error
4 0x00000C 0x00010C Math Error
5 0x00000E 0x00010E Reserved
6 0x000010 0x000110 Reserved
7 0x000012 0x000112 Reserved