Datasheet

 2011-2012 Microchip Technology Inc. DS70652E-page 95
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
7.0 INTERRUPT CONTROLLER
The interrupt controller reduces the numerous periph-
eral interrupt request signals to a single interrupt
request signal to the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104 CPU. It has
the following features:
• Up to eight processor exceptions and software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
7.1 Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location,
000004h. The IVT contains 126 vectors consisting of
eight non-maskable trap vectors, plus up to 118 sources
of interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit-wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 will take priority over interrupts at any
other vector address.
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices implement up to 26 unique
interrupts and 4 nonmaskable traps. These are
summarized in Tabl e 7-1 and Table 7-2.
7.1.1 ALTERNATE INTERRUPT VECTOR
TAB LE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a way to
switch between an application and a support environ-
ment without requiring the interrupt vectors to be
reprogrammed. This feature also enables switching
between applications to facilitate evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2 Reset Sequence
A device Reset is not a true exception because the inter-
rupt controller is not involved in the Reset process. The
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices clear their registers in
response to a Reset, forcing the PC to zero. The Digital
Signal Controller then begins program execution at
location, 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 41. “Interrupts
(Part IV)” (DS70300) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.