Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 370  2011-2012 Microchip Technology Inc.
Revision D (April 2012)
This revision includes updates in support of the
following new devices:
• dsPIC33FJ32GP101
• dsPIC33FJ32GP102
• dsPIC33FJ32GP104
• dsPIC33FJ32MC101
• dsPIC33FJ32MC102
• dsPIC33FJ32MC104
Also, where applicable, new sections were added to
peripheral chapters that provide information and links
to the related resources, as well as helpful tips. For
examples, see Section 18.1 “UART Helpful Tips”
and Section 18.2 “UART Resources”.
This revision includes text and formatting changes that
were incorporated throughout the document.
All other major changes are referenced by their
respective section in Table A-3.
TABLE A-3: MAJOR SECTION UPDATES
Section Name Update Description
“16-Bit Digital Signal
Controllers (up to 32-
Kbyte Flash and 2-Kbyte
SRAM)”
The content on the first page of this section was extensively reworked to provide the
reader with the key features and functionality of this device family in an “at-a-glance”
format.
TABLE 2: “dsPIC33FJ32(GP/MC)101/102/104 Device Features” was added, which
provides a feature overview of the new devices.
All pin diagrams were updated (see “Pin Diagrams”).
Section 1.0 “Device
Overview”
Updated the notes in the device family block diagram (see Figure 1-1).
Updated the following pinout I/O descriptions (Ta b l e 1- 1 ):
•ANx
• CNx
•RAx
• RCx
•C
VREFIN (formerly CVREF)
Relocated 1.1 “Referenced Sources” to the previous chapter (see “Referenced
Sources”).
Section 2.0 “Guidelines
for Getting Started with
16-bit Digital Signal
Controllers”
Updated the Recommended Minimum Connection diagram (see Figure 2-1).
Section 4.0 “Memory
Organization”
Updated the existing Program Memory Map (see Figure 4-1) and added the Program
Memory Map for dsPIC33FJ16(GP/MC)101/102 Devices (see Figure 4-1).
Updated the existing Data Memory Map (see Figure 4-4) and added the Data Memory
Map for dsPIC33FJ32(GP/MC)101/102/104 Devices with 2-Kbyte RAM (see Figure 4-5).
The following Special Function Register maps were updated or added:
• TABLE 4-5: Change Notification Register Map for dsPIC33FJ32(GP/MC)104
Devices
• TABLE 4-6: Interrupt Controller Register Map
• TABLE 4-8: Timers Register Map for dsPIC33FJ32(GP/MC)10X Devices
• TABLE 4-15: ADC1 Register Map for dsPIC33FJXX(GP/MC)101 Devices
• TABLE 4-17: ADC1 Register Map for dsPIC33FJ32(GP/MC)104 Devices
• TABLE 4-22: Peripheral Pin Select Input Register Map
• TABLE 4-26: Peripheral Pin Select Output Register Map for dsPIC33FJ32(GP/
MC)104 Devices
• TABLE 4-28: PORTA Register Map for dsPIC33FJ32(GP/MC)101/102 Devices
• TABLE 4-29: PORTA Register Map for dsPIC33FJ32(GP/MC)104 Devices
• TABLE 4-36: PORTC Register Map for dsPIC33FJ32(GP/MC)104 Devices
• TABLE 4-39: PMD Register Map