Datasheet
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 368 2011-2012 Microchip Technology Inc.
Revision C (June 2011)
This revision includes the following global update:
• All JTAG references have been removed
All other major changes are referenced by their
respective section in Table A - 2 .
In addition, minor text and formatting changes were
incorporated throughout the document.
TABLE A-2: MAJOR SECTION UPDATES
Section Name Update Description
High-Performance, Ultra Low Cost
16-bit Digital Signal Controllers
The TMS, TDI, TDO, and TCK pin names were removed from these pin
diagrams:
• 28-pin SPDIP/SOIC/SSOP
• 28-pin QFN
• 36-pin TLA
Section 1.0 “Device Overview” Updated the Buffer Type to Digital for the CTED1 and CTED2 pins (see
Table 1-1).
Section 4.0 “Memory Organization” Updated the SFR Address for IC2CON, IC3BUF, and IC3CON in the Input
Capture Register Map (see Table 4-7).
Added the VREGS bit to the RCON register in the System Control Register
Map (see Table 4-27).
Section 6.0 “Resets” Added the VREGS bit to the RCON register (see Register 6-1).
Section 8.0 “Oscillator Configuration” Updated the definition for COSC<2:0> = 001 and NOSC<2:0> = 001 in
the OSCCON register (see Register 8-1).
Section 15.0 “Motor Control PWM
Module”
Updated the title for Example 15-1 to include a reference to the Assembly
language.
Added Example 15-2, which provides a C code version of the write-
protected register unlock and Fault clearing sequence.
Section 19.0 “10-bit Analog-to-Digital
Converter (ADC)”
Updated the CH0 section and added Note 2 in both ADC block diagrams
(see Figure 19-1 and Figure 19-2).
Updated the multiplexer values in the ADC Conversion Clock Period Block
Diagram (see Figure 19-3.
Added the 01110 bit definitions and updated the 01101 bit definitions for
the CH0SB<4:0> and CH0SA<4:0> bits in the AD1CHS0 register (see
Register 19-5).
Section 22.0 “Charge Time
Measurement Unit (CTMU)”
Removed Section 22.1 “Measuring Capacitance”, Section 22.2 “Measuring
Time”, and Section 22.3 “Pulse Generation and Delay”
Updated the key features.
Added the CTMU Block Diagram (see Figure 22-1).
Updated the ITRIM<5:0> bit definitions and added Note 1 to the CTMU
Current Control register (see Register 22-3).