Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 DS70652E-page 260 Preliminary  2011-2012 Microchip Technology Inc.
The Configuration Shadow register map is shown in Table 2 3 -1.
The Configuration Flash Word maps are shown in Table 2 3 -2 and Table 23-3.
TABLE 23-2: CONFIGURATION FLASH WORDS FOR dsPIC33FJ16(GP/MC)10X DEVICES
(1)
TABLE 23-3: CONFIGURATION FLASH WORDS FOR dsPIC33FJ32(GP/MC)10X DEVICES
(1)
TABLE 23-1: CONFIGURATION SHADOW REGISTER MAP
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
F80004 FGS
— — — — — — GCP GWRP
F80006 FOSCSEL IESO PWMLOCK
(1)
— WDTWIN<1:0> FNOSC<2:0>
F80008 FOSC FCKSM<1:0> IOL1WAY
— —OSCIOFNC POSCMD<1:0>
F8000A FWDT FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
F8000C FPOR PWMPIN
(1)
HPOL
(1)
LPOL
(1)
ALTI2C1 — — — —
F8000E FICD Reserved
(2)
— Reserved
(3)
Reserved
(3)
— —ICS<1:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: These bits are available in dsPIC33FJ(16/32)MC10X devices only.
2: This bit is reserved for use by development tools.
3: These bits are reserved, program as ‘0’.
File
Name
Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2 002BFC
—IESOPWMLOCK
(2)
PWMPIN
(2)
WDTWIN<1:0> FNOSC<2:0> FCKSM<1:0> OSCIOFNC IOL1WAY LPOL
(2)
ALTI2C1 POSCMD<1:0>
CONFIG1 002BFE
— Reserved
(3)
Reserved
(3)
GCP GWRP Reserved
(4)
HPOL
(2)
ICS<1:0> FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
2: These bits are reserved on dsPIC33FJ16GP10X devices and read as ‘1’.
3: These bits are reserved, program as ‘0’.
4: This bit is reserved for use by development tools and must be programmed as ‘1’.
File
Name
Addr. Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2 0057FC
—IESOPWMLOCK
(2)
PWMPIN
(2)
WDTWIN<1:0> FNOSC<2:0> FCKSM<1:0> OSCIOFNC IOL1WAY LPOL
(2)
ALTI2C1 POSCMD<1:0>
CONFIG1 0057FE
— Reserved
(3)
Reserved
(3)
GCP GWRP Reserved
(4)
HPOL
(2)
ICS<1:0> FWDTEN WINDIS PLLKEN WDTPRE WDTPOST<3:0>
Legend: — = unimplemented, read as ‘1’.
Note 1: During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
2: These bits are reserved in dsPIC33FJ32GP10X devices and read as ‘1’.
3: These bits are reserved, program as ‘0’.
4: This bit is reserved for use by development tools and must be programmed as ‘1’.