Datasheet

 2011-2012 Microchip Technology Inc. DS70652E-page 217
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 19-2: ADC1 BLOCK DIAGRAM FOR dsPIC33FJXX(GP/MC)102 DEVICES
SAR ADC
S&H0
S&H1
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0-AN5
AN10
(3)
AN1
VREFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
CH123SA
VREFL
CH123SB
CH123NA
CH123NB
+
-
S&H2
AN1
AN4
CH123SA
VREFL
CH123SB
CH123NA
CH123NB
+
-
S&H3
AN2
AN5
CH123SA
VREFL
CH123SB
CH123NA
CH123NB
+
-
CH1
CH0
CH2
CH3
CH0SA<4:0>
Channel
Scan
CSCNA
Alternate Input Selection
VREFH VREFL
CTMU TEMP
(1)
Note 1: Internally connected to the CTMU module.
2: This selection is only used with CTMU capacitive and time measurement.
3: This pin is available in dsPIC33FJ32(GP/MC)102 devices only.
Open
(2)
CTMUI
(1)
AN9
(3)
AN10
(3)
AN9
(3)
AVDD
AVSS
VCFG<2:0>