Datasheet

dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102
DS80528B-page 4 © 2011 Microchip Technology Inc.
5. Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions
6. Module: CPU
When a previous DISI instruction is active (i.e.,
the DISICNT register is non-zero), and the value of
the DISICNT register is updated manually, the
DISICNT register freezes and disables interrupts
permanently.
Work around
Avoid updating the DISICNT register manually.
Instead, use the DISI #n instruction with the
required value for 'n'.
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS70652C):
None to report at this time.
A1
X
A1
X
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.