Datasheet

© 2011 Microchip Technology Inc. DS80528B-page 3
dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102
Silicon Errata Issues
1. Module: SPI
When using the frame sync pulse output feature
(FRMEN bit (SPIxCON2<15>) = 1) in Master
Mode (SPIFSD bit (SPIxCON2<14>) = 0), the
frame sync pulse is not being generated with an
active low pulse (FRMPOL bit (SPIxCON2<13>)
= 0).
Work around
The Slave Select pin is used as the frame sync
pulse when the frame sync pulse output feature is
used. Mapping the SSx input function and output
function to the same pad using the PPS feature
resolves this issue.
The code in Example 1 assigns SPI1 Slave Select
input and SPI1 Slave Select output to RP15.
EXAMPLE 1:
Affected Silicon Revisions
2. Module: SPI
When in SPI Slave mode (MSTEN bit
(SPIxCON1<5>) = 0) and using the frame sync
pulse output feature (FRMEN bit
(SPIxCON2<15>) = 1) in Slave Mode (SPIFSD bit
(SPIxCON2<14>) = 0), the Frame Sync Pulse
Edge Select bit must be set to ‘0’ (FRMDLY bit
(SPIxCON2 <1>) = 0)
Work around
There is no workaround. The Frame Sync Pulse
Edge Select bit cannot be set to produce a Frame
sync pulse that coincides with the first bit clock.
Affected Silicon Revisions
3. Module: UART
When using UTXISEL = 01 (Interrupt when last
character is shifted out of the Transmit Shift
Register), and the final character is being shifted
out through the Transmit Shift Register, the TX
interrupt may occur before the final bit is shifted
out.
Work around
If it is critical that the interrupt processing occurs
only when all transmit operations are complete,
after which the following work around can be
implemented:
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
transmit shift register empty bit, as shown in
Example 2.
EXAMPLE 2:
Affected Silicon Revisions
4. Module: UART
The transmitter write pointer does not get cleared
when the UART module is disabled
(UARTEN = 0), and it requires the TXEN bit to be
set in order to clear the write pointer.
Work around
Do not load data into the TX FIFO (register) before
setting the TXEN bit.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
A1
X
A1
X
/* Assign SPI1 Slave Select Input to RP15 */
RPINR21bits.SS1R = 15;
/* Assign peripheral output function SPI1
to RP15 */
RPOR7bits.RP15R = 0b01001;
A1
X
A1
X
// in UART1 initialization code
...
// Set to generate TX interrupt when all
// transmit operations are complete.
U1STAbits.UTXISEL0 = 1;
U1STAbits.UTXISEL1 = 0;
...
U1TXInterrupt(void)
{
// wait for the transmit buffer to be
// empty and then process interrupt.
while(U1STAbits.TRMT==0);
...