Information

 2012-2013 Microchip Technology Inc. DS80000540E-page 9
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
14. Module: PWM
In Center-Aligned Complementary mode with
independent time base, the PWM generator may
assert the PWMxH output for 100% of the duty
cycle. This has been observed when the value in
its PDCx register is less than one-half the value in
its ALTDTRx register.
Work around
Include a software routine to check that the duty
cycle value written to the PDCx register is always
at least one-half of the value in ALTDTRx.
Example 3 shows one way of doing this, with
PDCtemp representing the value to be written to
the PDCx register.
EXAMPLE 3:
Affected Silicon Revisions
15. Module: Comparator
The Digital Filter does not function per design
specification. When the FLTREN bit
(CMPCON<10>) is enabled, it will generate a
delay of approximately three cycles of the selected
clock source. This results in unwanted comparator
latency delay before changing the state of the
comparator output and any of the interrupts driven
by it.
Work around
The FLTREN bit (CMPCON <10>) should be reset
to ‘0’.
Affected Silicon Revisions
16. Module: PWM
When the PWMx generator is configured to
operate in Current Reset mode (XPRES
(PWMCONx<1>) = 1, Independent Time Base
mode (ITB (PWMCONx<9>) = 1)), the PWMx
Reset will happen only in every alternate PWM
cycle.
Work around
1. Generate an interrupt when the comparator
state changes. This interrupt should be high
priority and could be either a comparator
interrupt or PWMx Fault interrupt. The
current-limit interrupt does not function in
this mode. Inside the interrupt, update the
PHASEx (period value) with a value less
than the programmed duty cycle and then
immediately update the PHASEx register
with the value as required by the application
(PWM_period), as shown in Example 4.
EXAMPLE 4: WORK AROUND CODE
2. When the External Current Reset signal is
applied to the PWMx generator (configured
using the Current-Limit Control Signal
Source Select bits (CLSRC<4:0>) in the
PWMx Fault Current-Limit Control registers
(FCLCONx<14:10>), depending on the
PWM resolution selected (PCLKDIV<2:0>
(PTCON2<2:0>)), the maximum pulse
width of the External Current Reset signal is
to be restricted to less than the values as
shown in Table 1.
Affected Silicon Revisions
A1
X
A1
X
Altdtr_by2 = ALTDTRx / 2;
if (PDCtemp < Altdtr_by2)
{
PDCx = Altdtr_by2;
}
else
{
PDCx = PDCtemp;
}
TABLE 1: MAXIMUM EXTERNAL
CURRENT RESET SIGNAL
WIDTH
PCLKDIV<2:0>
Max. External Current Reset
Signal Width (ns)
000 20
001 40
010 80
011 160
100 320
101 640
110 1280
111 2560
A1
X
PWMx ISR:
{
PHASEx = PDCx - 100;
PHASEx = PWM_period;
PWMxIF = 0;
}