Information

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS80000540E-page 6  2012-2013 Microchip Technology Inc.
7. Module: SPI
When the SPI module is configured in Framed Mas-
ter mode and the Frame Sync Pulse Edge Select bit
(FRMDLY) is set to ‘1’, transmitting a word and then
buffering another word in the SPIxBUF register,
before the transmission has completed, results in
an incomplete transmission of the first data word.
Only the first 15 bits from the first data word are
transmitted, followed by the Sync Pulse and the
complete second word.
Work around
Between the two back-to-back SPI operations,
add a delay to ensure that the first word is fully
transmitted before the second word is written to
the SPIxBUF register, as shown in Example 2.
EXAMPLE 2:
Affected Silicon Revisions
8. Module: SPI
When in SPI Slave mode (SPIxCON1<MSTEN> = 0)
and using the Frame Sync Pulse output
feature (SPIxCON2<FRMEN> = 1) in Slave mode
(SPIxCON2<SPIFSD> = 0), the Frame Sync
Pulse Edge Select bit must be set to ‘0’
(SPIxCON2 <FRMDLY> = 0).
Work around
There is no work around. The Frame Sync Pulse
Edge Select bit cannot be set to produce a Frame
Sync Pulse that coincides with the first bit clock.
Affected Silicon Revisions
9. Module: UART
When using UTXISEL<1:0> = 01 (interrupt when
last character is shifted out of the Transmit Shift
Register) and the final character is being shifted
out through the Transmit Shift Register, the
Transmit (TX) Interrupt may occur before the final
bit is shifted out.
Work around
If it is critical that the interrupt processing occur
only when all transmit operations are complete,
hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
Affected Silicon Revisions
10. Module: UART
The Transmitter Write Pointer does not get cleared
when the UART module is disabled (UARTEN = 0),
and it requires the TXEN bit to be set in order to clear
the Write Pointer.
Work around
Do not load data into the TX FIFO (register) before
setting the TXEN bit.
Affected Silicon Revisions
11. Module: Comparator
When the Comparator module is enabled
(CMPON = 1), the output of the comparator is set
high for approximately 300 ns, regardless of the
comparator input signal level.
Work around
Allow at least 1 µs after the Comparator module is
enabled (CMPON = 1) to initiate any comparator
driven interrupts or Faults.
Affected Silicon Revisions
A1
X
A1
X
SPI1BUF = 0x0001;
while (SPI1STATbits.SPITBF);
asm("REPEAT #50");.
asm("NOP");
// The number of NOPs depends on the SPI
// clock prescalers
SPI1BUF = 0x0002;
A1
X
A1
X
A1
X