Information

 2012-2013 Microchip Technology Inc. DS80000540E-page 5
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
4. Module: PWM
The high-speed PWM module can operate with
variable period, duty cycle, dead-time and phase
values. The master period and other timing
parameters can be updated in the same PWM
cycle. With immediate updates disabled, the new
values should take effect at the start of the next
PWM cycle.
As a result of this erratum, the updated master
period takes effect on the next PWM cycle, while
the update of the additional timing parameter is
delayed by one PWM cycle. The parameters
affected by this erratum are as follows:
Master Period Registers: Update effective on the
next PWM cycle:
• PTPER: If PWMCONx<MTBS> = 0
• STPER: If PWMCONx<MTBS> = 1
Additional PWM Timing Parameters: Update
effective one PWM cycle after master period
update:
• Duty Cycle: PDCx, SDCx and MDC registers
• Phase: PHASEx or SPHASEx registers
• Dead Time: DTRx and ALTDTRx registers
and dead-time compensation signals
• Clearing of current-limit and Fault conditions,
and application of External Period Reset
signal
Work around
If the application requires the master period and
other parameters to be updated at the same time,
enable both immediate updates:
• PTCON<EIPU> = 1 to enable immediate
period updates
• PWMCONx<IUE> = 1 to enable immediate
updates of additional parameters listed above
Enabling immediate updates will allow updates to
the master period and the other parameter to take
effect immediately after writing to the respective
registers.
Affected Silicon Revisions
5. Module: PWM
If the PWM Clock Divider Select register
(PTCON2) is not equal to zero, the PWM module
may or may not initialize from an override state,
even when the Override Enable bits are set
(OVRENH = 1 or OVRENL = 1).
Work around
When configuring the Override Enable bits,
OVRENH and OVRENL (IOCONx<9,8>), set
these bits implicitly using word format; do not set
them explicity using bit format.
That is, use this format:
IOCON1 = IOCON1 & 0xFCFF
and not this format:
IOCON1bits.OVRENH = 1
Affected Silicon Revisions
6. Module: CPU
When the VREGS bit (RCON<8>) is set to a logic
‘0’ and the device enters Sleep mode, the device
cannot wake up.
Work around
Ensure that the VREGS bit (RCON<8>) is set to a
logic ‘1’ for device Sleep mode operation.
Affected Silicon Revisions
A1
X
A1
X
A1
X