Information

 2012-2013 Microchip Technology Inc. DS80000540E-page 3
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Silicon Errata Issues
1. Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always become set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions
2. Module: CPU
When a previous DISI instruction is active (i.e.,
the DISICNT register is non-zero), and the value of
the DISICNT register is updated manually, the
DISICNT register freezes and disables interrupts
permanently.
Work around
Avoid updating the DISICNT register manually.
Instead, use the DISI #n instruction with the
required value for ‘n’.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
A1
X
A1
X