Information

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS80000540E-page 2  2012-2013 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item # Issue Summary
Affected
Revisions
(1)
A1
CPU Instruction Set 1. When using the div.sd instruction, the overflow bit is
not getting set when an overflow occurs.
X
CPU Interrupt Disable 2. When a previous DISI instruction is active (i.e., the
DISICNT register is non-zero), and the value of the
DISICNT register is updated manually, the DISICNT
register freezes and disables interrupts permanently.
X
PWM PWM Module
Enable
3. A glitch may be observed on the PWM pins when the
PWM module is enabled after assignment of pin
ownership to the PWM module.
X
PWM Master Time
Base Mode
4. Writing to the Period register, and any other timing
parameter of the PWM module, will cause the update of
the other timing parameter to take effect, one PWM cycle
after the period update is effective.
X
PWM PWM Module
Enable
5.
If the PWM Clock Divider Select Register, PTCON2, is
not equal to zero, the PWM module may or may not
initialize from an override state
X
CPU Sleep Mode 6. When the VREGS bit (RCON<8>) is set to a logic ‘0’,
and the device enters into Sleep mode, the device
cannot wake-up.
X
SPI Frame Sync 7. In Framed Master mode and the Frame Sync Pulse
Edge Select bit (FRMDLY) is set to ‘1’, transmitting a
word and then buffering another word in the SPIxBUF
register, before the transmission has completed, results
in an incomplete transmission of the first data word.
X
SPI Frame Sync 8. In SPI Slave mode, with the Frame Sync pulse set as an
input, FRMDLY must be set to ‘0’.
X
UART TX Interrupt 9. A Transmit (TX) Interrupt may occur before the data
transmission is complete.
X
UART UARTEN 10. The Transmitter Write Pointer does not get cleared when
the UART is disabled (UARTEN = 0); it requires TXEN to
be set in order to clear the Write Pointer.
X
Comparator Comparator
Output
11. A glitch may occur on the comparator output when the
comparator module is enabled (CMPON = 1).
X
Comparator External
Reference
12. Comparator and DACOUT do not function when
EXTREF is enabled and EXTREF input voltage is less
than 1.6V.
X
PWM Immediate
Update
13. Dead time is not asserted when PDCx is updated to
cause an immediate transition on the PWMxH and
PWMxL outputs.
X
PWM Center-Aligned
Mode
14. PWMxH is asserted for 100% of the PWM period in
Complementary mode under certain circumstances.
X
Comparator Filter 15. The digital filter does not function per design
specification.
X
PWM Current Reset
Mode
16. In Current Reset mode, the PWM Reset only happens in
every alternate PWM cycle.
X
PWM External Period
Reset Mode
17. PWM period is reset if the External Period Reset signal is
still asserted at the end of the PWM ON time.
X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.