Information

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS80000540E-page 12  2012-2013 Microchip Technology Inc.
3. Module: Oscillator Configuration
The values describing the range of tenability of the
internal oscillator in Register 8-4 have been
corrected. The correct values are shown in bold
below:
REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER
(2)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TUN<5:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
(1)
011111 = Center frequency + 1.45% (7.478 MHz)
011110 = Center frequency + 1.40% (7.4743 MHz)
•
•
•
000001 = Center frequency + 0.047% (7.3734 MHz)
000000 = Center frequency (7.37 MHz)
111111 = Center frequency -0.047% (7.366 MHz)
•
•
•
100001 = Center frequency -1.453% (7.263 MHz)
100000 = Center frequency -1.5% (7.26 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither
characterized nor tested.
2: This register is reset only on a Power-on Reset (POR).