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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 16-Bit 40 null I/O number 21

 2012-2013 Microchip Technology Inc. DS80000540E-page 1

dsPIC33FJ06GS001/101A/102A/202A

and dsPIC33FJ09GS302

The dsPIC33FJ06GS001/101A/102A/202A and

dsPIC33FJ09GS302 family devices that you have

received conform functionally to the current Device

Data Sheet (DS75018C), except for the anomalies

described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be

addressed in future revisions of the

dsPIC33FJ06GS001/101A/102A/202A and

dsPIC33FJ09GS302 silicon.

Data Sheet clarifications and corrections start on Page 11,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 3 or

PICkit™ 3:

1. Using the appropriate interface, connect the device

to the MPLAB ICD 3 programmer/debugger or

PICkit 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device

, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The Device and Revision ID values for the

various dsPIC33FJ06GS001/101A/102A/202A and

dsPIC33FJ09GS302 silicon revisions are shown in

Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A1).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

dsPIC33FJ06GS001 0x4900

0x3001

dsPIC33FJ06GS101A 0x4901

dsPIC33FJ06GS102A 0x4904

dsPIC33FJ06GS202A 0x4905

dsPIC33FJ09GS302 0x4906

Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in

program memory.

2: Refer to the “dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits”

(DS70659) for detailed information on Device and Revision IDs for your specific device.

dsPIC33FJ06GS001/101A/102A/202A and

dsPIC33FJ09GS302 Family Silicon Errata

and Data Sheet Clarification

Summary of content (20 pages)

PAGE 1
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Family Silicon Errata and Data Sheet Clarification The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 family devices that you have received conform functionally to the current Device Data Sheet (DS75018C), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 3 or PICkit™ 3: 1.
PAGE 2
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item # Issue Summary Affected Revisions(1) A1 CPU Instruction Set 1. When using the div.sd instruction, the overflow bit is not getting set when an overflow occurs. X CPU Interrupt Disable 2. When a previous DISI instruction is active (i.e.
PAGE 3
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A1). 1. Module: CPU When using the Signed 32-by-16-bit Division instruction, div.sd, the overflow bit does not always become set when an overflow occurs. 2.
PAGE 4
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3. Module: PWM 2. Assign pin ownership to the GPIO module by configuring the PENH bit (IOCONx<15>) = 0 and the PENL bit (IOCONx<14>) = 0. 3. Specify the PWM override state to the desired safe state for the PWM pins using the OVRDAT<1:0> bit field in the IOCONx register. 4. Override the PWM outputs by setting the OVRENH bit (IOCONx<9>) = 1 and the OVRENL bit (IOCONx<8>) = 1. 5. Enable the PWM module by setting the PTEN bit (PTCON<15>) = 1. 6.
PAGE 5
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4. Module: PWM The high-speed PWM module can operate with variable period, duty cycle, dead-time and phase values. The master period and other timing parameters can be updated in the same PWM cycle. With immediate updates disabled, the new values should take effect at the start of the next PWM cycle.
PAGE 6
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 7. Module: SPI When the SPI module is configured in Framed Master mode and the Frame Sync Pulse Edge Select bit (FRMDLY) is set to ‘1’, transmitting a word and then buffering another word in the SPIxBUF register, before the transmission has completed, results in an incomplete transmission of the first data word. Only the first 15 bits from the first data word are transmitted, followed by the Sync Pulse and the complete second word.
PAGE 7
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 12. Module: Comparator The comparator and DAC modules do not function when both of the following are true: • the External Voltage Reference is selected (EXTREF = 1), and • the external voltage reference is less than 1.6V. Work around Use the INTREF or AVDD/2 references, whenever possible. If the External Voltage Reference must be used, be aware that the published specifications for EXTREF define an input voltage range of 0V minimum and (AVDD – 1.
PAGE 8
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 1: TIMING DIAGRAMS FOR CENTER-ALIGNED AND EDGE-ALIGNED MODES Period Period PTMRx PHASEx PTMRx PHASEx 0 0 PWMxH PWMxH PDCOLD PDCOLD PWMxL PWMxL PWMxH PWMxH PDCNEW > PDCOLD PDCNEW > PDCOLD PWMxL PWMxL PWMxH PWMxH PDCNEW < PDCOLD PDCNEW < PDCOLD PWMxL PWMxL Center-Aligned Mode DS80000540E-page 8 Edge-Aligned Mode  2012-2013 Microchip Technology Inc.
PAGE 9
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 14. Module: PWM 16. Module: PWM In Center-Aligned Complementary mode with independent time base, the PWM generator may assert the PWMxH output for 100% of the duty cycle. This has been observed when the value in its PDCx register is less than one-half the value in its ALTDTRx register.
PAGE 10
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 17. Module: PWM When External Period Reset mode is enabled, a Reset signal, asserted during the PWM ON time, and that continues to be asserted afterwards, will cause the PWM period to be reset immediately after the end of the PWM ON time. The expected behavior is for the External Reset Signal to be ignored if it is still active at the end of the PWM ON time.
PAGE 11
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS75018C): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Electrical Characteristics The Min. and Typ. values in Table 25-42 have been corrected.
PAGE 12
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3. Module: Oscillator Configuration The values describing the range of tenability of the internal oscillator in Register 8-4 have been corrected.
PAGE 13
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4. Module: High-Speed, 10-Bit Analog-to-Digital Converter (ADC) In Figure 19-2 and Figure 19-3, AN13 has been added and the number of output registers has been changed from eight to seven. In Figure 19-5, the number of output registers has been changed from eight to ten.
PAGE 14
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-3: ADC BLOCK DIAGRAM FOR THE dsPIC33FJ06GS102A DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 Seven 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN4 AN5 AN13 (INTREF)(1) Note 1: AN13 (INTREF) is an internal analog input and is not available on a pin. DS80000540E-page 14  2012-2013 Microchip Technology Inc.
PAGE 15
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-5: ADC BLOCK DIAGRAM FOR THE dsPIC33FJ09GS302 DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 SAR Core Ten 16-Bit Registers Bus Interface AN12(1) (EXTREF) Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN4 AN5 AN6 AN7 AN13(2) (INTREF) Note 1: 2: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference.
PAGE 16
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 5. Module: Electrical Characteristics In Table 25-43, the text for the Characteristics of DA13 (VRANGE) and DA14 (VLRANGE) is corrected as follows (changes in bold): • for DA13, Current Drive of 300 µA • for DA14, Current Drive of 50 µA 6. Module: Packaging A new packaging type, Ultra-Thin Quad Flat Pack No Lead, 6 mm x 6 mm x 0.5 mm (UQFN), was added for the dsPIC33FJ09GS302 28-pin device.
PAGE 17
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 APPENDIX A: REVISION HISTORY Rev A Document (3/2012) Initial release of this document; issued for revision A0 silicon. Included silicon issues 1 (CPU), 2 (CPU), 3 (GPIO), 4 (PGEC2/PGED2 Programming Pins (dsPIC33FJ06GS001/101A/102A Devices Only)), 5-9 (PWM), 10 (Sleep Mode), 11 (Sleep Mode), 12 (SPI), 13 (SPI), 14 (UART), 15 (UART), 16 (Comparator), and 17 (Comparator).
PAGE 18
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS80000540E-page 18  2012-2013 Microchip Technology Inc.
PAGE 19
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 20
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