Information

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS80000439N-page 6  2009-2013 Microchip Technology Inc.
5. Module: PWM
When PWM module is operated in
Complementary, Redundant and Push-pull output
modes, with Independent Time Base (ITB = 1) and
Independent Fault mode (IFLTMOD = 1) enabled,
the PWMxH and PWMxL outputs should be
affected by the Fault and Current-Limit events as
follows:
• PWMxH is affected by Current-Limit source
(FCLCON<CLSRC>) and the Current-Limit
should be reset at the end of the primary local
time base.
• PWMxL is affected by Fault source
(FCLCON<FLTSRC>) and the Fault should be
reset at the end of the primary local time base.
On silicon revisions affected by this erratum, the
Current-Limit event works correctly for the PWMxH
pin. However, the Fault event is reset by the
secondary local time base although it is not used to
generate the time base value. As a result, the Fault
event on PWMxL pin may not work as expected.
This erratum only applies to the cycle-by-cycle Fault
mode (FLTMOD = 0b01).
Work around
If PWM is in Complementary, Redundant or Push-
Pull mode and (ITB = 1), set SPHASEx to have the
same value as PHASEx. This will ensure that the
Fault event on the PWMxL pin is reset at the start
of the new PWM period for cycle-by-cycle
independent Fault operation.
Affected Silicon Revisions
6. Module: PWM
The independent time base PWM outputs may not
be synchronized with the Master time base PWM
outputs when both modes are used
simultaneously.
Work around
To synchronize the Independent PWM outputs
with the Master time base PWM outputs, disable
the Immediate Update Enable bit (IUE = 0), ensure
that the three Least Significant bits of the period
are zero, and that the duty cycle is between 8 ns
and the period minus 0x8.
This work around will not work if the frequency of
the PWM module is being updated on the fly.
Affected Silicon Revisions
7. Module: PWM
In PWM Latched Fault mode, the PWM outputs
may be latched on both the rising as well as the
falling edge of the Fault signal, regardless of the
Fault input polarity selection (set with the
FCLCONx<FLTPOL> bit setting).
Work around
None.
Affected Silicon Revisions
8. Module: PWM
A bit write to the CLMOD bit (bit 8) in the
FCLCONx register or consecutive writes to the
lower byte and higher byte of the FCLCONx
register, causes all other bits of the high byte to be
loaded with zeros.
Work around
Use Word writes for the FCLCONx register instead
of bit or byte writes.
Affected Silicon Revisions
A2 A3 A4
XX
X
A2 A3 A4
XX
X
A2 A3 A4
XX
X
A2 A3
A4
XX
X