Information

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS80000439N-page 16  2009-2013 Microchip Technology Inc.
43. Module: PWM
If the PWM is configured for Complimentary mode
and the SWAP bit is enabled, the PWM outputs
might operate as Redundant mode when the
PHASE value is greater than the programmed
dead-time (DTRx) value.
Work around
Using true independent output mode with the
independent Time Base mode bit (ITB) set to ‘0’,
the PWMx module can be configured to replicate
the original complementary signal by properly
setting up the phase (PHASEx, SPASEx) and the
independent duty cycle (PDCx, SDCx).
Affected Silicon Revisions
44. Module: PWM
The PWMx current-limit operation allows the
PWMx module to set/reset the output signals when
a specific current limit is detected with a minimum
latency delay. When operating the PWMx module
in Complementary mode (PMOD = 0), positive
dead time, and with Current-Limit Interrupt Enable
(CLIEN = 1), a less than 8-ns pulse glitch on the
complementary output may be present right after
the current limit is detected. This glitch, if present,
will occur prior to the implementation of the dead
time.
Work around
In order to avoid the <8 ns glitch to be propagated
into the MOSFET gate driver, a low-pass filter
(e.g., resistor-capacitor network) should be
implemented between the dsPIC
®
DSC PWMx
output pin and the gate driver IC input pin.
Affected Silicon Revisions
45. Module: PWM
The PWMx generator may not assert dead time on
the edges of transitions. This has been observed
when all of the following conditions are present:
• The PWMx generator is configured to operate
in Complementary mode with the
independent time base or master time base;
• Immediate update is enabled; and
• The value in the PDCx register is updated in
such a manner that the PWMxH and PWMxL
outputs make an immediate transition.
The current duty cycle, PDC
OLD, newly calculated
duty cycle, PDC
NEW, and the point at which the
write to the Duty Cycle register occurs within the
PWMx time base, will determine if the PWMxH and
PWMxL outputs make an immediate transition.
PWMxH and PWMxL outputs make an immediate
transition if the Duty Cycle register is written with a
new value, PDC
NEW, at a point of time when the
PWMx time base is counting a value that is in
between PDC
NEW and PDCOLD. Additionally,
writing to the Duty Cycle register close to the
instant of time where dead time is being applied
may result in reduced dead time, effective on the
PWMxH and PWMxL transition edges.
In Figure 1 (following page), if the duty cycle write
occurred in the shaded box, then PWMxH and
PWMxL will make an immediate transition without
dead time.
Work around
None. However, in most applications the duty
cycle update timing can be controlled using the
TRIGx trigger or Special Event Trigger such that
the above mentioned conditions are avoided
altogether.
Affected Silicon Revisions
A2 A3 A4
XX
X
A2 A3
A4
XX
X
A2 A3 A4
XX
X