Datasheet
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 30 2011-2012 Microchip Technology Inc.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
FLTA1
(1,2,4)
FLTB1
(3,4)
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
I
I
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
No
No
No
No
No
No
No
No
PWM1 Fault A input.
PWM1 Fault B input.
PWM1 Low Output 1
PWM1 High Output 1
PWM1 Low Output 2
PWM1 High Output 2
PWM1 Low Output 3
PWM1 High Output 3
RTCC O Digital No RTCC Alarm output.
CTPLS
CTED1
CTED2
O
I
I
Digital
Digital
Digital
Yes
No
No
CTMU pulse output.
CTMU External Edge Input 1.
CTMU External Edge Input 2.
CV
REFIN
CVREFOUT
C1INA
C1INB
C1INC
C1IND
C1OUT
C2INA
C2INB
C2INC
C2IND
C2OUT
C3INA
C3INB
C3INC
C3IND
C3OUT
I
O
I
I
I
I
O
I
I
I
I
O
I
I
I
I
O
Analog
Analog
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
No
No
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
Yes
Comparator Voltage Positive Reference Input.
Comparator Voltage Positive Reference Output.
Comparator 1 Positive Input A.
Comparator 1 Negative Input B.
Comparator 1 Negative Input C.
Comparator 1 Negative Input D.
Comparator 1 Output.
Comparator 2 Positive Input A.
Comparator 2 Negative Input B.
Comparator 2 Negative Input C.
Comparator 2 Negative Input D.
Comparator 2 Output.
Comparator 3 Positive Input A.
Comparator 3 Negative Input B.
Comparator 3 Negative Input C.
Comparator 3 Negative Input D.
Comparator 3 Output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1
pin on dsPIC33FJXXMC101 (20-pin) devices.
2: The FLTA1
pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only.
3: The FLTB1
pin is available in dsPIC(16/32)MC102/104 devices only.
4: The PWM Fault pins are enabled during any Reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM Faults.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
6: This pin is available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.