Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 206  2011-2012 Microchip Technology Inc.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware sets or clears when Start, Repeated Start or Stop is detected.
bit 2 R_W: Read/Write Information bit (when operating as I
2
C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware sets or clears after reception of an I
2
C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware sets when I2CxRCV is written with received byte. Hardware clears when software reads
I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware sets when software writes to I2CxTRN. Hardware clears at completion of data transmission.
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)