Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104

DS70652E-page 204  2011-2012 Microchip Technology Inc.

bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I

C slave)

Used in conjunction with the SCLREL bit.

1 = Enables software or receives clock stretching

0 = Disables software or receives clock stretching

bit 5 ACKDT: Acknowledge Data bit (when operating as I

C master, applicable during master receive)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1 = Sends NACK during Acknowledge

0 = Sends ACK during Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I

C master, applicable during master receive)

1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; hardware

clears at end of master Acknowledge sequence

0 = Acknowledge sequence is not in progress

bit 3 RCEN: Receive Enable bit (when operating as I

C master)

1 = Enables Receive mode for I

C; hardware clears at end of eighth bit of the master receive data byte.

0 = Receive sequence is not in progress

bit 2 PEN: Stop Condition Enable bit (when operating as I

C master)

1 = Initiates Stop condition on SDAx and SCLx pins; hardware clears at end of the master Stop sequence

0 = Stop condition not in progress

bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I

C master)

1 = Initiates Repeated Start condition on SDAx and SCLx pins; hardware clears at end of the master

Repeated Start sequence

0 = Repeated Start condition is not in progress

bit 0 SEN: Start Condition Enable bit (when operating as I

C master)

1 = Initiates Start condition on SDAx and SCLx pins; hardware clears at end of master Start sequence

0 = Start condition is not in progress