Datasheet

 2011-2012 Microchip Technology Inc. DS70652E-page 177

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104

14.2 Output Compare Control Register

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

— —OCSIDL — — — — —

bit 15 bit 8

U-0 U-0 U-0 R-0, HC R/W-0 R/W-0 R/W-0 R/W-0

— — — OCFLT OCTSEL OCM<2:0>

bit 7 bit 0

Legend: HC = Hardware Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 OCSIDL: Stop Output Compare in Idle Mode Control bit

1 = Output Compare x will halt in CPU Idle mode

0 = Output Compare x will continue to operate in CPU Idle mode

bit 12-5 Unimplemented: Read as ‘0’

bit 4 OCFLT: PWM Fault Condition Status bit

1 = PWM Fault condition has occurred (cleared in hardware only)

0 = No PWM Fault condition has occurred

(This bit is only used when OCM<2:0> = 111.)

bit 3 OCTSEL: Output Compare Timer Selection bit

1 = Timer3 is the clock source for Output Compare x

0 = Timer2 is the clock source for Output Compare x

bit 2-0 OCM<2:0>: Output Compare Mode Select bits

111 = PWM mode on OCx, Fault pin is enabled

110 = PWM mode on OCx, Fault pin is disabled

101 = Initializes OCx pin low, generates continuous output pulses on OCx pin

100 = Initializes OCx pin low, generates single output pulse on OCx pin

011 = Compare event toggles OCx pin

010 = Initializes OCx pin high, compare event forces OCx pin low

001 = Initializes OCx pin low, compare event forces OCx pin high

000 = Output compare channel is disabled