Datasheet

 2011-2012 Microchip Technology Inc. DS70652E-page 171
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 12-4: T5CON CONTROL REGISTER
(1)
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON
(3)
—TSIDL
(2)
— — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0
— TGATE
(3)
TCKPS<1:0>
(3)
— —TCS
(3)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TON: Timer5 On bit
(3)
1 = Starts 16-bit Timer3
0 = Stops 16-bit Timer3
bit 14 Unimplemented: Read as ‘0’
bit 13 TSIDL: Timer5 Stop in Idle Mode bit
(2)
1 = Discontinues timer operation when device enters Idle mode
0 = Continues timer operation in Idle mode
bit 12-7 Unimplemented: Read as ‘0’
bit 6 TGATE: Timer5 Gated Time Accumulation Enable bit
(3)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer5 Input Clock Prescale Select bits
(3)
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer5 Clock Source Select bit
(3)
1 = External clock from T5CK pin
0 = Internal clock (F
OSC/2)
bit 0 Unimplemented: Read as ‘0’
Note 1: This register is available in dsPIC33FJ32(GP/MC)10X devices only.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timer4 Control register (T4CON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
3: When the 32-bit timer operation is enabled (T32 = 1) in the Timer4 Control register (T4CON<3>), these
bits have no effect.