Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 144  2011-2012 Microchip Technology Inc.
TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
10.4.3 CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices include
three features to prevent alterations to the peripheral
map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
10.4.3.1 Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these regis-
ters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 0x46 to OSCCON<7:0>.
2. Write 0x57 to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
10.4.3.2 Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a Configuration Mismatch Reset will
be triggered.
10.4.3.3 Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<5>) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute, and the Peripheral Pin Select Control
registers cannot be written to. The only way to clear the
bit and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
Peripheral Pin Select registers.
Function RPnR<4:0> Output Name
NULL 00000 RPn tied to Default Port Pin
C1OUT 00001 RPn tied to Comparator 1 Output
C2OUT 00010 RPn tied to Comparator 2 Output
U1TX 00011 RPn tied to UART1 Transmit
U1RTS
00100 RPn tied to UART1 Ready-to-Send
SCK1 01000 RPn tied to SPI Clock
(1)
SDO1 00111 RPn tied to SPI Data Output
(1)
SS1 01001 RPn tied to SPI1 Slave Select Output
(1)
OC1 10010 RPn tied to Output Compare 1
OC2 10011 RPn tied to Output Compare 2
CTPLS 11101 RPn tied to CTMU Pulse Output
C3OUT 11110 RPn tied to Comparator 3 Output
Note 1: This function is available in dsPIC33FJ32(GP/MC)10X devices only.
Note: MPLAB
®
C30 provides built-in C language
functions for unlocking the OSCCON
register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See MPLAB IDE Help for more
information.