Datasheet

 2011-2012 Microchip Technology Inc. DS70652E-page 111
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
— —CTMUIE— — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — U1EIE FLTB1IE
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 CTMUIE: CTMU Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-2 Unimplemented: Read as ‘0’
bit 1 U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 FLTB1IE: PWM1 Fault B Interrupt Enable bit
(1)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Note 1: This bit is available in dsPIC(16/32)MC102/104 devices only.