Datasheet

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70652E-page 110  2011-2012 Microchip Technology Inc.
REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
— —IC3IE— — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4-0 Unimplemented: Read as ‘0’
REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 U-0
FLTA1IE
(1)
RTCIE — — — —PWM1IE
(1)
—
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14 RTCIE: RTCC Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-10 Unimplemented: Read as ‘0’
bit 9 PWM1IE: PWM1 Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8-0 Unimplemented: Read as ‘0’
Note 1: This bit is available in dsPIC(16/32)MC10X devices only.