Datasheet

dsPIC33FJ12MC201/202

Section 19.0 “10-bit/12-bit

Analog-to-Digital Converter

(ADC)”

Updated ADC Conversion Clock Select bits in the AD1CON3 register from

ADCS<5:0> to ADCS<7:0>. Any references to these bits have also been

updated throughout this data sheet (Register 19-3).

Replaced Figure 19-1 (ADC1 Module Block Diagram for dsPIC33FJ12MC201)

and added Figure 19-2 (ADC1 Block Diagram for dsPIC33FJ12MC202).

Removed Equation 19-1: ADC Conversion Clock Period and Figure 19-2: ADC

Transfer Function (10-Bit Example).

Added Note 2 to Figure 19-2: ADC Conversion Clock Period Block Diagram.

Updated ADC1 Input Channel 1, 2, 3 Select Register (see Register 19-4) as

follows:

• Changed bit 10-9 (CH123NB - dsPIC33FJ12MC201 devices only)

description for bit value of 10 (if AD12B = 0).

• Updated bit 8 (CH123SB) to reflect device-specific information.

• Updated bit 0 (CH123SA) to reflect device-specific information.

• Changed bit 2-1 (CH123NA - dsPIC33FJ12MC201 devices only)

description for bit value of 10 (if AD12B = 0).

Updated ADC1 Input Channel 0 Select Register (see Register 19-5) as follows:

• Changed bit value descriptions for bits 12-8

• Changed bit value descriptions for bits 4-0 (dsPIC33FJ12MC201 devices)

Modified Notes 1 and 2 in the ADC1 Input Scan Select Register Low (see

Modified Notes 1 and 2 in the ADC1 Port Configuration Register Low (see

Section 20.0 “Special Features” Added FICD register information for address 0xF8000E in the Device

Configuration Register Map (see Table 20-1).

Added FICD register content (BKBUG, COE, JTAGEN, and ICS<1:0> to the

dsPIC33FJ12MC201/202 Configuration Bits Description (see Table 20-2).

Added a note regarding the placement of low-ESR capacitors, after the second

paragraph of Section 20.2 “On-Chip Voltage Regulator” and to Figure 20-2.

Removed the words “if enabled” from the second sentence in the fifth paragraph

of Section 20.3 “BOR: Brown-out Reset”

TABLE 25-1: MAJOR SECTION UPDATES

Section Name Update Description