Datasheet

© 2007-2011 Microchip Technology Inc. DS70265E-page 161
dsPIC33FJ12MC201/202
REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1
(2)
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PMOD3 PMOD2 PMOD1
bit 15 bit 8
U-0 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— PEN3H
(1)
PEN2H
(1)
PEN1H
(1)
— PEN3L
(1)
PEN2L
(1)
PEN1L
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 PMOD4:PMOD1: PWM I/O Pair Mode bits
1 = PWM I/O pin pair is in the Independent PWM Output mode
0 = PWM I/O pin pair is in the Complementary Output mode
bit 7 Unimplemented: Read as ‘0’
bit 6-4 PEN3H:PEN1H: PWMxH I/O Enable bits
(1)
1 = PWMxH pin is enabled for PWM output
0 = PWMxH pin disabled, I/O pin becomes general purpose I/O
bit 3 Unimplemented: Read as ‘0’
bit 2-0 PEN3L:PEN1L: PWMxL I/O Enable bits
(1)
1 = PWMxL pin is enabled for PWM output
0 = PWMxL pin disabled, I/O pin becomes general purpose I/O
Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in
the FPOR Configuration register.
2: PWM2 supports only one PWM I/O pin pair. PWM1 on dsPIC33FJ12MC201 devices supports only two
PWM I/O pin pairs.