Information

 2010-2012 Microchip Technology Inc. DS80461G-page 9
dsPIC33FJ12MC201/202
27. Module: QEI
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt should
be generated after an input pulse on the QEA
input. This interrupt is not generated in the affected
silicon.
Work around
None.
Affected Silicon Revisions
28. Module: QEI
When the TQCS and TQGATE bits in the
QEIxCON register are set, the POSCNT counter
should not increment but erroneously does, and if
allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while running the QEI in Timer Gated
Accumulation mode, initialize MAXCNT = 0.
Affected Silicon Revisions
29. Module: SPI
Regardless of the Slave setting for the Frame
delay bit (FRMDLY = 0 or FRMDLY = 1), the Slave
always acts as if the sync pulse precedes the first
SPI data bit (FRMDLY = 0). The SPI will not
function as described if Slave FRMDLY = 1.
Work around
None.
Affected Silicon Revisions
30. Module: ADC
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
PD) may exceed the specifications listed
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around 1:
In order to remain within the IPD specifications
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV #0
instruction.
Work around 2:
If the ADC module was previously initialized and
enabled, before entering Sleep, execute the lines
of code provided in Example 2.
Affected Silicon Revisions
EXAMPLE 2:
A2 A3 A4 A5
XXX
X
A2 A3 A4
A5
XXX
X
A2 A3 A4
A5
XXX
X
Note: The ADC module must be reinitialized by
the user application before resuming ADC
operation.
Note: Unlike Work around 1, the user
application does not need to reinitialize
the ADC module; however, it is necessary
to re-enable the ADC module by setting
the ADON bit after waking from Sleep.
A2 A3 A4
A5
XXX
X
AD1CON1bits.ADON = 0; //Disable the ADC module
__asm__ volatile ("REPEAT #50"); //Wait 50 Tcy
__asm__ volatile ("NOP"); //Repeat NOP 51 times
Sleep(); // Execute PWRSAV #0 and go to Sleep