Information

 2010-2012 Microchip Technology Inc. DS80461G-page 3
dsPIC33FJ12MC201/202
I
2
C — 19. With the I
2
C module enabled, the port bits and external
interrupt input functions (if any) associated with SCL
and SDA pins do not reflect the actual digital logic levels
on the pins.
XXXX
I
2
C 10-bit
Addressing
20. The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Signifi-
cant bits (LSbs) of the address are the same as the 7-bit
reserved addresses.
XXXX
I
2
C — 21. After the ACKSTAT bit is set when receiving a NACK, it
may be cleared by the reception of a Start or Stop bit.
XXXX
CPU EXCH
Instruction
22. The EXCH instruction does not execute correctly. X X X X
PWM Debug Mode 23. PTMR does not keep counting down after halting code
execution in Debug mode.
XXXX
PWM DOZE Mode 24. The Motor Control PWM module generates more
interrupts than expected when DOZE mode is used and
the output postscaler value is different than 1:1.
XXXX
QEI Interrupts 25. The QEI module does not generate an interrupt in a
particular overflow condition.
XXXX
UART Break
Character
Generation
26. The UART module will not generate back-to-back Break
characters.
XXXX
QEI Timer Gated
Accumulation
Mode
27. When Timer Gated Accumulation is enabled, the QEI
does not generate an interrupt on every falling edge.
XXXX
QEI Timer Gated
Accumulation
Mode
28. When Timer Gated Accumulation is enabled, and an
external signal is applied, the POSCNT increments and
generates an interrupt after a match with MAXCNT.
XXXX
SPI Slave
FRMDLY
29. The SPI communication in Framed mode does not func-
tion correctly if the Slave SPI frame delay bit (FRMDLY)
is set to ‘1’.
XXXX
ADC Current
Consumption
in Sleep
Mode
30. If the ADC module is in an enabled state when the
device enters Sleep mode, the power-down current
(I
PD) of the device may exceed the device data sheet
specifications.
XXXX
CPU div.sd 31. When using the div.sd instruction, the overflow bit is
not getting set when an overflow occurs.
XXXX
UART TX Interrupt 32. A transmit (TX) Interrupt may occur before the data
transmission is complete.
XXXX
JTAG Flash
Programming
33. JTAG Flash programming is not supported. X X X X
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature
Item
Number
Issue Summary
Affected
Revisions
(1)
A2 A3 A4 A5
Note 1: Only those issues indicated in the last column apply to the current silicon revision.